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    SRAM 128 X 8 Search Results

    SRAM 128 X 8 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MD2114A-5 Rochester Electronics LLC SRAM Visit Rochester Electronics LLC Buy
    27S03ADM/B Rochester Electronics LLC 27S03A - SRAM Visit Rochester Electronics LLC Buy
    29705/BXA Rochester Electronics LLC 29705 - SRAM Visit Rochester Electronics LLC Buy
    29705APCB Rochester Electronics LLC 29705A - SRAM Visit Rochester Electronics LLC Buy
    27S03ALM/B Rochester Electronics LLC 27S03A - SRAM Visit Rochester Electronics LLC Buy

    SRAM 128 X 8 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    M68Z128

    Abstract: M68Z128W TSOP32 3VE1
    Text: M68Z128W 3V, 1 Mbit 128 Kbit x 8 Low Power SRAM with Output Enable FEATURES SUMMARY • ULTRA LOW DATA RETENTION CURRENT Figure 1. Package – 10nA (typical) – 2.0µA (max) ■ OPERATION VOLTAGE: 3.0V (+0.6 / –0.3V) ■ 128 Kbit x 8 SRAM WITH OUTPUT ENABLE


    Original     		PDF M68Z128W TSOP32 M68Z128 M68Z128W TSOP32 3VE1

    M68Z128

    Abstract: TSOP32
    Text: M68Z128 5V, 1 Mbit 128 Kbit x 8 Low Power SRAM with Output Enable FEATURES SUMMARY • ULTRA LOW DATA RETENTION CURRENT Figure 1. Package – 10nA (typical) – 2.0µA (max) ■ OPERATION VOLTAGE: 5.0V ± 10% ■ 128 Kbit x 8 VERY FAST SRAM WITH OUTPUT ENABLE


    Original     		PDF M68Z128 TSOP32 M68Z128 TSOP32

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-00208 Spec Title: CY7C1324H 2-MBIT 128K X 18 FLOW-THROUGH SYNC SRAM Sunset Owner: Jayasree Nayar (njy) Replaced by: NONE CY7C1324H 2-Mbit (128 K x 18) Flow-Through Sync SRAM 2-Mbit (128 K × 18) flow-through Sync SRAM


    Original     		PDF CY7C1324H CY7C1324H

    M48Z129V

    Abstract: M48Z129Y
    Text: M48Z129Y* M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original     		PDF M48Z129Y* M48Z129V 32-pin PMDIP32 M48Z129Y: M48Z129V: M48Z129V M48Z129Y

    M48Z129V

    Abstract: M48Z129Y
    Text: M48Z129Y* M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original     		PDF M48Z129Y* M48Z129V 32-pin PMDIP32 M48Z129Y: M48Z129V: M48Z129V M48Z129Y

    M48Z129V

    Abstract: M48Z129Y
    Text: M48Z129Y M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original     		PDF M48Z129Y M48Z129V 32-pin PMDIP32 M48Z129Y: M48Z129V: M48Z129V M48Z129Y

    M48Z128

    Abstract: M48Z128V M48Z128Y SOH28 TSOP32
    Text: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original     		PDF M48Z128 M48Z128Y, M48Z128V* 32-pin M48Z128: M48Z128Y: M48Z128V: M48Z128 M48Z128V M48Z128Y SOH28 TSOP32

    SOH28

    Abstract: TSOP32 M48Z128 M48Z128V M48Z128Y
    Text: M48Z128 M48Z128Y, M48Z128V 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original     		PDF M48Z128 M48Z128Y, M48Z128V M48Z128: M48Z128Y: M48Z128V: 28-PIN 32LEAD SOH28 TSOP32 M48Z128 M48Z128V M48Z128Y

    Untitled

    Abstract: No abstract text available
    Text: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original     		PDF M48Z128 M48Z128Y, M48Z128V* 32-pin M48Z128: M48Z128Y: M48Z128V: 28-PIN 32-LEAD

    M40Z300

    Abstract: M48Z128 M48Z128V M48Z128Y D 4242 CP1621
    Text: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES


    Original     		PDF M48Z128 M48Z128Y, M48Z128V* M48Z128: M48Z128Y: M48Z128V: M40Z300 M48Z128 M48Z128V M48Z128Y D 4242 CP1621

    Untitled

    Abstract: No abstract text available
    Text: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original     		PDF M48Z128 M48Z128Y, M48Z128V* M48Z128: M48Z128Y: M48Z128V: 28-PIN 32-LEADd

    M48Z128

    Abstract: M48Z128V M48Z128Y M40Z300
    Text: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original     		PDF M48Z128 M48Z128Y, M48Z128V* 32-pin M48Z128: M48Z128Y: M48Z128V: M48Z128 M48Z128V M48Z128Y M40Z300

    M40Z300

    Abstract: M48Z128 M48Z128V M48Z128Y SOH28
    Text: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES


    Original     		PDF M48Z128 M48Z128Y, M48Z128V* M48Z128: M48Z128Y: M48Z128V: M40Z300 M48Z128 M48Z128V M48Z128Y SOH28

    Untitled

    Abstract: No abstract text available
    Text: M48Z129V 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of


    Original     		PDF M48Z129V

    M48Z128

    Abstract: M48Z128V M48Z128Y AN1012
    Text: M48Z128 M48Z128Y, M48Z128V 5.0 V or 3.3 V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of


    Original     		PDF M48Z128 M48Z128Y, M48Z128V M48Z128: M48Z128Y: M48Z128V: PMDIP32 M48Z128 M48Z128V M48Z128Y AN1012

    5716

    Abstract: M48Z129V M48Z129Y
    Text: M48Z129Y M48Z129V 5.0 V or 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of


    Original     		PDF M48Z129Y M48Z129V M48Z129Y: 5716 M48Z129V M48Z129Y

    E-2-WEI

    Abstract: 32-PIN ZL23
    Text: M K 48127/128 N ,X -55/70/85 SGSTHOMSON V # IM Û M lL IÛ T r M « ! 1 MEG (1,048,576-BIT) 128 K X 8 CMOS SRAM ADVANCE DATA BYTEWYDE 128K X 8 CMOS SRAM EQUAL CYCLE/ACCESS TIMES, 55,70,85NS PIN CONNECTION MAX 600 mil. Plastic DIP LOW Vcc DATA RETENTION 2 VOLTS


    OCR Scan     		PDF MK48127/128 576-BIT) 32-PIN MK48127 A0-A16 E-2-WEI ZL23

    A6W 4d

    Abstract: SRAM 6T MT58LC256K18G1 mt 1898 le
    Text: ADVANCE 256K x 18. 128K x 32/36 2.5V I/O, PIPELINED. SCD SYNCBURST SRAM I^ IIC R a N MT 58 LC 256 K 18 G 1 , M T 58 LC 128 K32 G 1, MT 58 LC 128 K36 G 1 SYNCBURST SRAM 3.3V Supply, +2.5V I/O, Pipelined, Burst Counter and Single-Cycle Deselect SYNCBURST SRAM


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: POSTACI 5 • 'T :¿tL-Z3>rlLf MK48127/128 N,X -55/70/85 SCS-THOMSON •[L tM M tsM O S S G S-TH O M SO N 3QE d 1 MEG ( 1-,048,576-BIT) 128 K X 8 CMOS SRAM ADVANCE DATA ■ BYTEWYDE 128K X 8 CM O S SRAM ■ EQUAL CYCLE/ACCESS TIMES, 55,70,85NS MAX. ■ LOW V cc DATA RETENTION 2 VOLTS


    OCR Scan     		PDF MK48127/128 576-BIT) 32-PIN K48127

    Untitled

    Abstract: No abstract text available
    Text: rz 7 Ä 7# S G S -T H O M S O N iM û îE im iO T M O S MK48127/128 N,X -55/70/85 1 MEG ( 1-,048,576-BIT) 128 K X 8 CMOS SRAM A D V A N C E DATA • BYTEWYDE 128K X 8 CM OS SRAM ■ EQUAL CYCLE/ACCESS TIMES, 55,70,85NS MAX ■ LOW Vcc DATA RETENTION 2 VOLTS


    OCR Scan     		PDF MK48127/128 576-BIT) 32-PIN MK48127

    BA22

    Abstract: BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 MCF5204
    Text: SECTION 5 SRAM 5.1 SRAM FEATURES • 512-Byte SRAM, Organized as 128 x 32 Bits • Single-Cycle Access • Physically Located on Processor's High-Speed Local Bus • Byte, Word, Longword Address Capabilities • Memory Mapping Defined by the Customer 5.2 SRAM OPERATION


    OCR Scan     		PDF 512-Byte 0-modulo-512 MCF5204 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30

    24 volt 300 AH

    Abstract: No abstract text available
    Text: MICRON SEMICONDUCTOR INC b7E D • blllSMT 00GTMa3 481 ■ MRN ADVANCE MT5 LC 1008 X 8 SRAM M IC R O N B 128 K SEM ICON DUCTORIN C. SRAM 1 2 8 K x 8 SRAM LOW VOLTAGE WITH OUTPUT ENABLE • All I/O pins are 5V tolerant • High speed: 15,17, 20, 25,35 and 45ns


    OCR Scan     		PDF 00GTMa3 32-Pin 24rolled) MT5LC1008 24 volt 300 AH

    BA30

    Abstract: BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 MCF5206
    Text: SECTION 5 SRAM 5.1 SRAM FEATURES • 512-Byte SRAM, Organized as 128 x 32 Bits • Single-Cycle Access • Physically Located on ColdFire core's High-Speed Local Bus • Byte, Word, Longword Address Capabilities • Memory Mapping Defined by the Customer 5.2 SRAM OPERATION


    OCR Scan     		PDF 512-Byte 0-modulo-512 MCF5206 BA30 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29

    Untitled

    Abstract: No abstract text available
    Text: 5EP -? intol ¡FX780 10 ns FLEXIogic FPGA FAMILY WITH SRAM OPTION Any CFB can be either 24V10 Logic or SRAM Block — Up to 80 Complex Macrocells — 128 x 10 SRAM Configuration — CFB Selectable 3.3V or 5V Outputs — Open-Drain Output Option High Performance FPGA Field


    OCR Scan     		PDF FX780 24V10 12-Bit