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Fairchild Semiconductor Corporation 54H101FMQB
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Quest Components	54H101FMQB		4			1 $27.689 10 $27.689 100 $27.689 1000 $27.689 10000 $27.689	Buy Now

54H101FM Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
54H101FM		Fairchild Semiconductor	JK Edge Triggered Flip-Flop		Scan	PDF

54H101FM Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
74H101 Abstract: No abstract text available Text: n a t i o n a l s e n I c o n d -clogio 0 2 e d I b s o n a B Got377s 3 I T -^ 6 -0 7 '0 7 101 CO N N ECTIO N DIAGRAM S PINO UT A 54H/74H101 JK EDGE-TRIGGERED FLIP-FLOP (with A N D - O R Inputs D ESC R IP TIO N — The '101 is a high speed J K negative edge-triggered flipflop. The AND-OR gate inputs are inhibited while the clock input is LOW.	OCR Scan	PDF	Got377s 54H/74H101 54/74H 74H101
IC LA 4138 Abstract: No abstract text available Text: 101 CONNECTION DIAGRAMS P IN O U T A 54H/74H101 0 JK EDGE-TRIGGERED FLIP-FLOP with A N D -O R Inputs DESCRIPTION — The '101 is a high speed J K negative edge-triggered flipflop. The A N D -O R gate inputs are inhibited w hile the clo ck input is LOW. When the clo ck goes HIGH, the inputs are enabled and data will be accepted.	OCR Scan	PDF	54H/74H101 54/74H IC LA 4138
100414DC Abstract: 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501 Text: FAIRMONT ELECTRONICS PTY. LTD. TE L.48-6421 4 8 -6 4 8 1 /2 /4 C AB LES ' FAIRTRONICS' C R A IG H A L L T E L E X 8-3227 S A . P O .BOX 41102, C R A IG H A LL 2024. I ouani v-ox 39! 262Bramley 2018 FAIRCHILD 464 Ellis Street, M ountain View, C alifornia 94042	OCR Scan	PDF	262Bramley orporation/464 962-5011/TWX 19-PIN 100414DC 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501
74H101 Abstract: 54H101 54H101FM 74H101DC 74H101FC 74H101PC 74hcl Text: 101 CO N N ECTIO N DIAGRAMS P IN O U T A 54H/74H101 0 JK EDGE-TRIGGERED FLIP-FLOP with AND-OR Inputs D E S C R IP T IO N — The '101 is a high speed J K negative edge-triggered flip flop. T he A N D-O R gate inputs are inhibited while the clock input is LOW.	OCR Scan	PDF	54H/74H101 54/74H 74H101 54H101 54H101FM 74H101DC 74H101FC 74H101PC 74hcl