74H101DC Search Results

74H101DC Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
74H101DC		Fairchild Semiconductor	JK Edge Triggered Flip-Flop		Scan	PDF

74H101DC Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
74H101 Abstract: No abstract text available Text: n a t i o n a l s e n I c o n d -clogio 0 2 e d I b s o n a B Got377s 3 I T -^ 6 -0 7 '0 7 101 CO N N ECTIO N DIAGRAM S PINO UT A 54H/74H101 JK EDGE-TRIGGERED FLIP-FLOP (with A N D - O R Inputs D ESC R IP TIO N — The '101 is a high speed J K negative edge-triggered flipflop. The AND-OR gate inputs are inhibited while the clock input is LOW.	OCR Scan	PDF	Got377s 54H/74H101 54/74H 74H101
1n52408 Abstract: 1N52428 zener SFC2311 78M12HM 21L02A 54175 IRS 9530 transistor 10116dc BB105G 962PC Text: Contents Fairchild Semiconductors Ltd. Solid State Scientific Inc. Diodes Ltd. Thomson C. S. F. B Ashcroft Electronics Ltd. Sprague Electric UK Ltd. Precision Dynamic Corp. B&R Relays Schrack Relays Heller mann Electric B Foreword We are pleased to present the latest edition of the BARLEC Catalogue, which	OCR Scan	PDF	301PT1115 302PT1115 303PT1115 311PT1110 312PTI110 319PTI110 327PTI110 351PT1115 353PT1115 1n52408 1N52428 zener SFC2311 78M12HM 21L02A 54175 IRS 9530 transistor 10116dc BB105G 962PC
IC LA 4138 Abstract: No abstract text available Text: 101 CONNECTION DIAGRAMS P IN O U T A 54H/74H101 0 JK EDGE-TRIGGERED FLIP-FLOP with A N D -O R Inputs DESCRIPTION — The '101 is a high speed J K negative edge-triggered flipflop. The A N D -O R gate inputs are inhibited w hile the clo ck input is LOW. When the clo ck goes HIGH, the inputs are enabled and data will be accepted.	OCR Scan	PDF	54H/74H101 54/74H IC LA 4138
100414DC Abstract: 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501 Text: FAIRMONT ELECTRONICS PTY. LTD. TE L.48-6421 4 8 -6 4 8 1 /2 /4 C AB LES ' FAIRTRONICS' C R A IG H A L L T E L E X 8-3227 S A . P O .BOX 41102, C R A IG H A LL 2024. I ouani v-ox 39! 262Bramley 2018 FAIRCHILD 464 Ellis Street, M ountain View, C alifornia 94042	OCR Scan	PDF	262Bramley orporation/464 962-5011/TWX 19-PIN 100414DC 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501
74H101 Abstract: 54H101 54H101FM 74H101DC 74H101FC 74H101PC 74hcl Text: 101 CO N N ECTIO N DIAGRAMS P IN O U T A 54H/74H101 0 JK EDGE-TRIGGERED FLIP-FLOP with AND-OR Inputs D E S C R IP T IO N — The '101 is a high speed J K negative edge-triggered flip flop. T he A N D-O R gate inputs are inhibited while the clock input is LOW.	OCR Scan	PDF	54H/74H101 54/74H 74H101 54H101 54H101FM 74H101DC 74H101FC 74H101PC 74hcl