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    XC9572 Price and Stock

    AMD XC9572XL-10VQG64C

    IC CPLD 72MC 10NS 64VQFP
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    DigiKey XC9572XL-10VQG64C Tray 132,356 1
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    AMD XC9572XL-10TQG100I

    IC CPLD 72MC 10NS 100TQFP
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    DigiKey XC9572XL-10TQG100I Tray 38,922 1
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    AMD XC9572XL-10VQG44C

    IC CPLD 72MC 10NS 44VQFP
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    DigiKey XC9572XL-10VQG44C Tray 33,657 1
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    Farnell XC9572XL-10VQG44C Each 2,927 53 Weeks, 1 Days 1
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    AMD XC9572XL-10VQG44I

    IC CPLD 72MC 10NS 44VQFP
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    DigiKey XC9572XL-10VQG44I Tray 4,484 1
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    AMD XC9572XL-7TQG100C

    IC CPLD 72MC 7.5NS 100TQFP
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    DigiKey XC9572XL-7TQG100C Tray 2,922 1
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    Farnell XC9572XL-7TQG100C Each 891 53 Weeks, 1 Days 1
    • 1 £15.61
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    XC9572 Datasheets (290)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    XC9572 Xilinx In-System Programmable CPLD Family Original PDF
    XC9572 Xilinx XC9572 In-System Programmable CPLD Original PDF
    XC9572 Xilinx The Programmable Logic Data Book Original PDF
    XC9572-10PC44 Xilinx XC9572 In-System Programmable CPLD Original PDF
    XC9572-10PC44C Xilinx In-system programmable CPLD. Speed 10ns pin-to-pin delay. Original PDF
    XC9572-10PC44C Xilinx In-System Programmable CPLD Original PDF
    XC9572-10PC44C Xilinx 72 MACROCELL 5 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC9572-10PC44C Xilinx Embedded - CPLDs (Complex Programmable Logic Devices), Integrated Circuits (ICs), IC CPLD 72MC 10NS 44PLCC Original PDF
    XC9572-10PC44C Xilinx Over 600 obsolete distributor catalogs now available on the Datasheet Archive - CPLDs XCR Series CPLDs - 3 V and 5 V Fast Zero Power CoolRunner Scan PDF
    XC9572-10PC44I Xilinx In-System Programmable CPLD Original PDF
    XC9572-10PC44I Xilinx In-System Programmable CPLD Original PDF
    XC9572-10PC44I Xilinx 72 MACROCELL 5 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC9572-10PC44I Xilinx Embedded - CPLDs (Complex Programmable Logic Devices), Integrated Circuits (ICs), IC CPLD 72MC 10NS 44PLCC Original PDF
    XC9572-10PC84C Xilinx In-System Programmable CPLD Original PDF
    XC9572-10PC84C Xilinx In-System Programmable CPLD Original PDF
    XC9572-10PC84C Xilinx 72 MACROCELL 5 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC9572-10PC84C Xilinx Embedded - CPLDs (Complex Programmable Logic Devices), Integrated Circuits (ICs), IC CPLD 72MC 10NS 84PLCC Original PDF
    XC9572-10PC84I Xilinx In-System Programmable CPLD Original PDF
    XC9572-10PC84I Xilinx Embedded - CPLDs (Complex Programmable Logic Devices), Integrated Circuits (ICs), IC CPLD 72MC 10NS 84PLCC Original PDF
    XC9572-10PC84I Xilinx In-System Programmable CPLD Original PDF
    ...

    XC9572 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    XC9572

    Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
    Text: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable


    Original     		PDF XC9572 DS065 36V18 XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C

    XC9572

    Abstract: XC9572 Family PC84 PQ100 XC9500 xc9572 tq100
    Text: 1 XC9572 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins


    Original     		PDF XC9572 36V18 44-Pin 84-Pin 100-Pin XC9572 PQ100 TQ100 XC9572 Family PC84 PQ100 XC9500 xc9572 tq100

    XC9572XL

    Abstract: xc9572xl pin PC44 XC9500XL XC9572 XC9572XL-10 XC9572XL-5 XC9572XL-7 VQ64 TQFP 100 footprint
    Text:  XC9572XL High Performance CPLD September 28, 1998 Version 1.0 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output


    Original     		PDF XC9572XL XC9500XL comprise48-Pin 64-Pin TQ100 100-Pin -40oC XC9572XL xc9572xl pin PC44 XC9572 XC9572XL-10 XC9572XL-5 XC9572XL-7 VQ64 TQFP 100 footprint

    XC9572

    Abstract: xc9572 data sheet XC9572-15PC84C XC9572-7PCG84C XC9572-15PQG100I XC9572-10PQ100C XC9572-7TQG100C XC9572-15PCG44C XC9572-10PQ100I XC9572-10PC44I
    Text: XC9572 In-System Programmable CPLD R DS065 v4.3 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable


    Original     		PDF XC9572 DS065 36V18 xc9572 data sheet XC9572-15PC84C XC9572-7PCG84C XC9572-15PQG100I XC9572-10PQ100C XC9572-7TQG100C XC9572-15PCG44C XC9572-10PQ100I XC9572-10PC44I

    XC9572

    Abstract: PC84 PQ100 XC9500
    Text: 1 XC9572 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins


    Original     		PDF XC9572 36V18 44-Pin 84-Pin 100-Pin XC9572 PQ100 TQ100 PC84 PQ100 XC9500

    PC44

    Abstract: VQ44 XAPP361 XC9500XV XC9572XV
    Text: XC9572XV High-performance CPLD R DS052 v2.5 August 21, 2003 5 Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins)


    Original     		PDF XC9572XV DS052 44-pin 48-pin 100-pin 72-user 54-input 220oC. PC44 VQ44 XAPP361 XC9500XV

    XC9572XL

    Abstract: xc9572xl pin configuration XC9572XL-5VQ44C XAPP114 XAPP427 XC9500XL XC9572 XC9572XL-10 XC9572XL-5 XC9572XL-7
    Text: XC9572XL High Performance CPLD R DS057 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC9572XL DS057 XC9500XL 220oC. xc9572xl pin configuration XC9572XL-5VQ44C XAPP114 XAPP427 XC9572 XC9572XL-10 XC9572XL-5 XC9572XL-7

    Untitled

    Abstract: No abstract text available
    Text: XC9572XL High Performance CPLD DS057 v1.1 August 28, 2000 5 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)


    Original     		PDF XC9572XL DS057 44-pin 48-pin 64-pin 100-pin TQ100 XC9572XL

    XC9572

    Abstract: XC9572-15PQG100C XC9572-10TQG100I XC9572-15TQG100C XC9572-10PQ100I XC9572 pcg84 XC9572-15PCG84C XC9572-10PQG100C XC9572-15PCG44C XC9572 PC84
    Text: XC9572 In-System Programmable CPLD R DS065 v4.3 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable


    Original     		PDF XC9572 DS065 36V18 XC9572-15PQG100C XC9572-10TQG100I XC9572-15TQG100C XC9572-10PQ100I XC9572 pcg84 XC9572-15PCG84C XC9572-10PQG100C XC9572-15PCG44C XC9572 PC84

    marking code f4 3 pin

    Abstract: No abstract text available
    Text: XC9572XV High-performance CPLD R DS052 v2.6 April 15, 2005 5 Product Specification Features • • • • • • • • PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)


    Original     		PDF XC9572XV DS052 XC9500XV 220oC. marking code f4 3 pin

    xc9572xl pin configuration

    Abstract: XC9572XL XC9572XL-7VQ44I DS057 xc9572xl pin XC9572XL-10CS48C XAPP114 XC9500XL XC9572 XC9572XL-10
    Text: XC9572XL High Performance CPLD R DS057 v1.4 August 21, 2003 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC9572XL DS057 XC9500XL 220oC. xc9572xl pin configuration XC9572XL-7VQ44I DS057 xc9572xl pin XC9572XL-10CS48C XAPP114 XC9572 XC9572XL-10

    XC95144XL-10TQG100C

    Abstract: XC9572XL-TQ100 XC9572XL xc95144xl XC9572XL TQ100 XC95144XL-10TQG144I XC95144XL-7TQG100C XC95144XL-10TQ100I xc95144xl tq144 XCN05003
    Text: Change in Wafer Fabrication Facility for XC95144XL and XC9572XL CPLDs XCN05003 v1.0 January 31, 2005 Product/Process Change Notice Overview The purpose of this notification is to communicate a change in the wafer fabrication facility for the XC95144XL and XC9572XL CPLD devices.


    Original     		PDF XC95144XL XC9572XL XCN05003 XC95144XL-10TQG100C XC9572XL-TQ100 XC9572XL TQ100 XC95144XL-10TQG144I XC95144XL-7TQG100C XC95144XL-10TQ100I xc95144xl tq144 XCN05003

    Untitled

    Abstract: No abstract text available
    Text: Product Obsolete/Under Obsolescence XC9572XV High-performance CPLD R 5 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9572XV devices with equivalent XC9572XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to


    Original     		PDF XC9572XV DS052 XC9500XV 220oC. XCN05020.

    Untitled

    Abstract: No abstract text available
    Text: XC9572XL High Performance CPLD R DS057 v1.5 July 15, 2004 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC9572XL DS057 XC9500XL 220oC.

    xc9572xl pin configuration

    Abstract: XC9572XL XC9572XL-7TQG100C XC9572XL-5VQG44C XAPP427 44 VQFP package 84 PLCC pin configuration XC9572XL-10TQ100C XC9572XL-7CSG48C XC9572XL-7VQ44I
    Text: XC9572XL High Performance CPLD R DS057 v1.6 September 15, 2004 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output


    Original     		PDF XC9572XL DS057 XC9500XL 220oC. xc9572xl pin configuration XC9572XL-7TQG100C XC9572XL-5VQG44C XAPP427 44 VQFP package 84 PLCC pin configuration XC9572XL-10TQ100C XC9572XL-7CSG48C XC9572XL-7VQ44I

    PC44

    Abstract: XC9500XL XC9572 XC9572XL XC9572XL-10 XC9572XL-5 XC9572XL-7 XC9572 VQ44
    Text: XC9572XL High Performance CPLD DS057 v1.1 August 28, 2000 5 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)


    Original     		PDF XC9572XL DS057 44-pin 48-pin 64-pin 100-pin TQ100 XC9572XL PC44 XC9500XL XC9572 XC9572XL-10 XC9572XL-5 XC9572XL-7 XC9572 VQ44

    SPARTAN-II xc2s200 pq208

    Abstract: XCR3256XL-12TQ144Q XC2S100-5FG256Q xc2s200 pq208 XC2S150 PQ208 XC2C256 vq100 xc9572xl10vq64q XC2S200-5FG456Q XC9536XL-10VQ44Q XC2S300E-6FT256Q
    Text: IQ SOLUTIONS FOR AUTOMOTIVE Global Clocks Pin to pin logic Delay ns Output Voltage Compatible Speed Grade (Q-Grade) Product term clocks per function block Macrocells VQ44 34 36 800 90 3.3/5 -15 3 15 18 3.3/5 XC9572-15TQ100Q TQ100 72 72 1600 90 3.3/5 -15


    Original     		PDF XC9572-15TQ100Q TQ100 XC9536XL-10VQ44Q XC9536XL-10VQ64Q XC9572XL-10VQ64Q XC9572XL-10TQ100Q XC2S400E-6FG456Q FG456 40x60 SPARTAN-II xc2s200 pq208 XCR3256XL-12TQ144Q XC2S100-5FG256Q xc2s200 pq208 XC2S150 PQ208 XC2C256 vq100 xc9572xl10vq64q XC2S200-5FG456Q XC9536XL-10VQ44Q XC2S300E-6FT256Q

    xc9572xl pin configuration

    Abstract: XC9572XL XC9572XL-10PCG44C XC9572XL-10CS48I XC9572XL-10VQG44C XC9572XL-7TQ100C XC9572XL-10PC44C xc9572xl-10PCG44C pin XC9572XL-7PCG44C XC9572XL-5TQG100C
    Text: XC9572XL High Performance CPLD R DS057 v2.0 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)


    Original     		PDF XC9572XL DS057 44-pin 48-pin 64-pin 100-pin 220oC. xc9572xl pin configuration XC9572XL-10PCG44C XC9572XL-10CS48I XC9572XL-10VQG44C XC9572XL-7TQ100C XC9572XL-10PC44C xc9572xl-10PCG44C pin XC9572XL-7PCG44C XC9572XL-5TQG100C

    mchp

    Abstract: XC9572 XC9572 PC84
    Text: HXILINX XC9572 In-System Programmable CPLD October 28, 1997 Version 2.0 Product Specification Features Operating current for each design can be approximated for specific operating conditions using the following equation: • • 7.5 ns pin-to-pin logic delays on all pins


    OCR Scan     		PDF XC9572 36V18 PQ100 TQ100 44-Pin 84-Pin 100-Pin PQ100 TQ100 mchp XC9572 PC84

    xc9572

    Abstract: PC84 84-Pin Plastic Leaded Chip Carrier
    Text: flXILINX XC9572 In-System Programmable CPLD January, 1997 Version 1.0 Prelim inary Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCN-|-to 125 MHz • • • 72 m acrocells with 1,600 usable gates Up to 72 user I/O pins


    OCR Scan     		PDF XC9572 36V18 84-Pin PQ100 100-Pin TQ100 TQ100 XC9572 PC84 84-Pin Plastic Leaded Chip Carrier

    Untitled

    Abstract: No abstract text available
    Text: flXIUNX XC9572 In-System Programmable CPLD October 28, 1997 Version 2.0 Product Specification Features Operating current for each design can be approximated for specific operating conditions using the following equation: • 7.5 ns pin-to-pin logic delays on all pins


    OCR Scan     		PDF XC9572 36V18 PQ100 TQ100 44-Pin 84-Pin 100-Pin XC9572

    C9572

    Abstract: No abstract text available
    Text: HXILINX XC9572XL High Performance CPLD September 28, 1998 Version 1.0 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depend­ ing on the system frequency, design application and output


    OCR Scan     		PDF XC9572XL 44-pin 48-pin 64-pin 100-Pin TQ100 C9572

    XC9572

    Abstract: XC9572 PC84
    Text: EXILINX XC9572 In-System Programmable CPLD June 1, 1996 Version 1.0 Advance Product Specification Features Description • The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four


    OCR Scan     		PDF XC9572 36V18 PQ100 TQ100 XC9572 PC84

    XC9572

    Abstract: No abstract text available
    Text: flXIU N X XC9572 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins fcN T 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins


    OCR Scan     		PDF XC9572 36V18 PQ100 TQ100 44-Pin 84-Pin 100-Pin lndustrial-40 PQ100