Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837
25-BIT
14-Bit
74SSTUB32866A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A w w w .t i.c om SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837A
25-BIT
14-Bit
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837A
25-BIT
14-Bit
74SSTUB32866A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837A
25-BIT
14-Bit
74SSTUB32866A
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SB866A
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837
25-BIT
14-Bit
74SSTUB32866A
SB866A
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74SSTUB32866A
Abstract: 74SSTUB32866AZKER D8-D13 Q11A Q13A
Text: 74SSTUB32866A www.ti.com SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837A
25-BIT
14-Bit
74SSTUB32866A
74SSTUB32866AZKER
D8-D13
Q11A
Q13A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837A
25-BIT
14-Bit
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SB865A
Abstract: SB866A ddr2 PLL JESD82 SSTUx32864 SSTU32868 JEDEC DDR2-400 2rx8 SB866 SN74SSTUB32866
Text: Application Report SCAA101 – March 2009 DDR2 Memory Interface Clocks and Registers – Overview Christian Schmoeller . CDC - Clock Distribution Circuits ABSTRACT This application report gives an overview of the existing JEDEC DDR2 Register and
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SCAA101
SB865A
SB866A
ddr2 PLL
JESD82
SSTUx32864
SSTU32868
JEDEC DDR2-400
2rx8
SB866
SN74SSTUB32866
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74SSTUB32866A
Abstract: 74SSTUB32866AZKER D8-D13 Q11A Q13A SB866A
Text: 74SSTUB32866A www.ti.com SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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Original
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74SSTUB32866A
SCAS837A
25-BIT
14-Bit
74SSTUB32866A
74SSTUB32866AZKER
D8-D13
Q11A
Q13A
SB866A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837
25-BIT
14-Bit
74SSTUB32866A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837A
25-BIT
14-Bit
74SSTUB32866A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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Original
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74SSTUB32866A
SCAS837A
25-BIT
14-Bit
74SSTUB32866A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2
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Original
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PDF
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74SSTUB32866A
SCAS837
25-BIT
14-Bit
74SSTUB32866A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32866A www.ti.com SCAS837 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2
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74SSTUB32866A
SCAS837
25-BIT
14-Bit
74SSTUB32866A
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