QXA11 Search Results

QXA11 Price and Stock

Filter by Manufacturer


SanDisk Corporation SDSQXA1-128G-GN6MA Extreme C10 Microsdhc 128Gb A2 U3 Rohs Compliant: Yes \|Sandisk SDSQXA1-128G-GN6MA (Alternate Part Number: 619659169688
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Newark	SDSQXA1-128G-GN6MA	Bulk			1	1 - 10 - 100 - 1000 - 10000 -	Buy Now
Western Digital Corp SDSQXA1-128G-AN6MA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
NAC	SDSQXA1-128G-AN6MA				1	1 - 10 - 100 - 1000 - 10000 -	Get Quote
SanDisk Corporation SDSQXA1-1T00-AN6MA Ext microSD W Adapter 1TB
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
NAC	SDSQXA1-1T00-AN6MA				1	1 - 10 - 100 - 1000 - 10000 -	Get Quote

QXA11 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
407 MTS controller Abstract: XLXX JESD8-11A pinout DDR3-1333 DDR3 rdimm pcb layout Text: DATASHEET Advanced Information SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description application. By disabling unused outputs the power consumption is reduced. This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock	Original	PDF	SSTE32882KA1 28-bit 26-bit 32882KA1 SSTE32882KA1 407 MTS controller XLXX JESD8-11A pinout DDR3-1333 DDR3 rdimm pcb layout
cK 7201 Abstract: SSTE32882 SSTE32882HLB xlxx transistor DA3 307 qbba1 dba1 DDR3 layout DDR3 pcb layout DDR3L Text: DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation. All inputs are 1.35V and 1.5V CMOS compatible, except the	Original	PDF	28-bit 26-bit SSTE32882HLB 32882HLB SSTE32882HLB cK 7201 SSTE32882 xlxx transistor DA3 307 qbba1 dba1 DDR3 layout DDR3 pcb layout DDR3L
INSSTE32882 Abstract: maxim dallas 2501 P16CV SY100EL16 SN65MLVD201 SN65EPT22 INCU877 INCUA877 ttl crystal oscillator using 7404 P16CV857B Text: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer	Original	PDF
Untitled Abstract: No abstract text available Text: DATASHEET 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation. All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the	Original	PDF	28-bit 26-bit 32882KB1 SSTE32882KB1
SSTL-15 Abstract: SN74SSTE32882 QxA11 DA11 SN74SSTE32882ZALR DDR3 pcb layout DDR3 sdram pcb layout guidelines QxA12 sstl_15 SSTL15 Text: SN74SSTE32882 www.ti.com SCAS840 – NOVEMBER 2006 28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair Differential Clock PLL Driver • FEATURES • • • • • Pinout Optimizes DDR3 DIMM PCB Layout 1-to-2 Register Outputs and 1-to-4 Clock Pair	Original	PDF	SN74SSTE32882 SCAS840 28-Bit 56-Bit SSTL-15 SN74SSTE32882 QxA11 DA11 SN74SSTE32882ZALR DDR3 pcb layout DDR3 sdram pcb layout guidelines QxA12 sstl_15 SSTL15
DDR3U Abstract: SSTE32882 2yn1 DDR3 rdimm pcb layout SSTE32882KA1 DDR3U-1600 da-15 pinout dba1 DDR3 layout DDR3 pcb layout Text: DATASHEET Advanced Information 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.	Original	PDF	28-bit 26-bit 32882KA1 SSTE32882KA1 DDR3U SSTE32882 2yn1 DDR3 rdimm pcb layout SSTE32882KA1 DDR3U-1600 da-15 pinout dba1 DDR3 layout DDR3 pcb layout
INSSTE32882 Abstract: maxim dallas 2501 insstua32866 INSSTU32864 INSSTU32866 ttl crystal oscillator using CIRCUIT DIAGRAM INCUA877 ps 2501 dallas GSM home automation block diagram INCU877 Text: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer	Original	PDF
SSTE32882KB1 Abstract: XLXX DDR3U-1600 QAA10 DDR3 rdimm pcb layout DDR3U QAA15 Text: DATASHEET 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation. All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the	Original	PDF	28-bit 26-bit 32882KB1 SSTE32882KB1 SSTE32882KB1 XLXX DDR3U-1600 QAA10 DDR3 rdimm pcb layout DDR3U QAA15
Untitled Abstract: No abstract text available Text: DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation. All inputs are 1.35V and 1.5V CMOS compatible, except the	Original	PDF	28-bit 26-bit SSTE328n 32882HLB SSTE32882HLB
SSTE32882KA1 Abstract: No abstract text available Text: DATASHEET Advanced Information 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.	Original	PDF	28-bit 26-bit 32882KA1 SSTE32882KA1 SSTE32882KA1
DDR3U Abstract: DDR3U-1866 SLGSSTE32882 top 261 yn JESD79-3 dba1 DDR3L DDR3-2133 RC10 RC11 Text: SLGSSTE32882 DDR3 Registering Clock Driver with Parity and Quad Chip Selects Features • 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity • Supports high density DDR3 modules • Quad Chip Selects • Supports 1.25V up to DDR3U-1866 , 1.35V (up to DDR3L-1866), and 1.5V (up to DDR3-2133)	Original	PDF	SLGSSTE32882 28-bit 26-bit DDR3U-1866) DDR3L-1866) DDR3-2133) 176-TFBGA 25hich DDR3U DDR3U-1866 SLGSSTE32882 top 261 yn JESD79-3 dba1 DDR3L DDR3-2133 RC10 RC11
SLGSSTE32882-A04B Abstract: DDR3U SLGSSTE32882 SLGSSTE32882-B04B DDR3L DDR3U-1333 ddr3 RDIMM pinout XLXX JESD79-3 RC10 Text: SLGSSTE32882 DDR3 Registering Clock Driver with Parity and Quad Chip Selects Features • 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity • Supports high density DDR3 modules • Quad Chip Selects • Supports 1.25V up to DDR3U-1333 , 1.35V (up to DDR3L-1333), and 1.5V (up to DDR3-1600)	Original	PDF	SLGSSTE32882 28-bit 26-bit DDR3U-1333) DDR3L-1333) DDR3-1600) 176-TFBGA 000-0032882-10g SLGSSTE32882-A04B DDR3U SLGSSTE32882 SLGSSTE32882-B04B DDR3L DDR3U-1333 ddr3 RDIMM pinout XLXX JESD79-3 RC10
XLXX Abstract: SSTE32882 dba1 SSTE32882HLB JESD8-11A Text: DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation. All inputs are 1.35V and 1.5V CMOS compatible, except the	Original	PDF	SSTE32882HLB 28-bit 26-bit SSTE32882Hd 32882HLB SSTE32882HLB XLXX SSTE32882 dba1 JESD8-11A
DDR3 rdimm pcb layout Abstract: SSTE32882KA1 XLXX SSTE32882 407 MTS controller LX-XX Text: DATASHEET Advanced Information SSTE32882KA1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description application. By disabling unused outputs the power consumption is reduced. This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock	Original	PDF	SSTE32882KA1 28-bit 26-bit SSTE32882HLBAKG SSTE32882HLBAKG8 SSTE32882HLBBKG SSTE32882HLBBKG8 SSTE32882KA1 19-Aug-2010 DDR3 rdimm pcb layout XLXX SSTE32882 407 MTS controller LX-XX