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    MTD64 Search Results

    MTD64 Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    MTD64 Fairchild Semiconductor Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs Original PDF

    MTD64 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    MTD64

    Abstract: No abstract text available
    Text: Revised April 2002 Package MTD64 64-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Package Number MTD64 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.


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    PDF MTD64 64-Lead MO-153, MTD64

    Q1B-Q13B

    Abstract: SSTV16859
    Text: Revised March 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible


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    PDF SSTV16859 13-Bit Q1B-Q13B

    SSTV16859

    Abstract: No abstract text available
    Text: Revised August 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible


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    PDF SSTV16859 13-Bit

    GTLP16T1655

    Abstract: GTLP16T1655MTD MTD64
    Text: Revised December 2000 GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls General Description Features The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It


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    PDF GTLP16T1655 16-Bit GTLP16T1655 GTLP16T1655MTD MTD64

    M24B SOT23

    Abstract: qsc 1110 GTLP16612 GTLP16616 GTLP16617 MQA20 MQA24 soic 16 Jedec package outline
    Text: Revised February 2001 Interface Products Ordering Information and Physical Dimensions Interface Products Ordering Information GTLP/USB Products Ordering Information Note: The GTLP16612, GTLP16616, GTLP16617 do not use the device type numbering scheme, please see datasheets for specific ordering information.


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    PDF GTLP16612, GTLP16616, GTLP16617 MS500144 M24B SOT23 qsc 1110 GTLP16612 GTLP16616 MQA20 MQA24 soic 16 Jedec package outline

    74VCX16722

    Abstract: 74VCX16722MTD MTD64 VCX16722
    Text: Revised January 2005 74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16722 low voltage 22-bit register contains twentytwo non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The design


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    PDF 74VCX16722 22-Bit VCX16722 74VCX16722 74VCX16722MTD MTD64

    GTLP16T1655

    Abstract: GTLP16T1655MTD MTD64
    Text: Revised April 2000 GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver General Description Features The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data


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    PDF GTLP16T1655 16-Bit GTLP16T1655 GTLP16T1655MTD MTD64

    VCX16722

    Abstract: 74VCX16722 74VCX16722MTD MTD64
    Text: Revised July 2000 74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16722 low voltage 22-bit register contains twentytwo non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The design


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    PDF 74VCX16722 22-Bit VCX16722 74VCX16722 74VCX16722MTD MTD64

    74ALVC16722

    Abstract: 74ALVC16722MTD ALVC16722 MTD64
    Text: Revised December 2001 74ALVC16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC16722 low voltage 22-bit register contains twenty-two non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The


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    PDF 74ALVC16722 22-Bit ALVC16722 74ALVC16722 74ALVC16722MTD MTD64

    mm74c922

    Abstract: nte CROSS-REFERENCE SJ 76 A DIODE EMI Quad 2 input nand gate cd 4093 7400 functional cross-reference HST 4047 pinout information of CMOS 4001, 4011, 4070 32-Bit Parallel-IN Serial-OUT Shift Register Fairchild Semiconductor Integrated Circuit Data Catalog 1970 application MM74C926
    Text: Logic Product Catalog Analog Discrete Interface & Logic Optoelectronics July 2002 Across the board. Around the world. Logic Literature Table of Contents Description Literature # Advanced Logic Products Databook CROSSVOLT , Fairchild Switch, TinyLogic™, VHC


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    PDF Power247TM, mm74c922 nte CROSS-REFERENCE SJ 76 A DIODE EMI Quad 2 input nand gate cd 4093 7400 functional cross-reference HST 4047 pinout information of CMOS 4001, 4011, 4070 32-Bit Parallel-IN Serial-OUT Shift Register Fairchild Semiconductor Integrated Circuit Data Catalog 1970 application MM74C926

    SSTV16859

    Abstract: No abstract text available
    Text: Preliminary Revised February 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset Preliminary General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The


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    PDF SSTV16859 13-Bit SSTV16859

    SSTV16859

    Abstract: MO-205 MTD64 SSTV16859G SSTV16859MTD
    Text: Revised January 2005 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible


    Original
    PDF SSTV16859 13-Bit SSTV16859 MO-205 MTD64 SSTV16859G SSTV16859MTD

    GTLP16T1655

    Abstract: GTLP16T1655MTD MTD64
    Text: Revised September 1999 GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver General Description Features The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data


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    PDF GTLP16T1655 16-Bit GTLP16T1655 GTLP16T1655MTD MTD64

    SSTV16859

    Abstract: MO-205 MTD64 SSTV16859GX SSTV16859MTD
    Text: Revised September 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible


    Original
    PDF SSTV16859 13-Bit SSTV16859 MO-205 MTD64 SSTV16859GX SSTV16859MTD

    SSTV16859

    Abstract: bga96 SSTV16859G MO-205 MTD64 SSTV16859MTD
    Text: Revised July 2002 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible


    Original
    PDF SSTV16859 13-Bit SSTV16859 bga96 SSTV16859G MO-205 MTD64 SSTV16859MTD

    iso 1043-1

    Abstract: DIN 6120 sae j1344 j1344 w28c iso 1043-1 polypropylene bga Shipping Trays MEC34 BGA OUTLINE DRAWING TSOP package tray
    Text: Packing Considerations Methods, Materials and Recycling Transport Media All NSC commercial devices are prepared, inspected and packed to insure proper physical support and protection during handling, transportation and shipment. Assembled devices are packed in one or more of the following container


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    PDF MS011809-4 MS011809-1 MS011809-5 MS011809-2 MS011809-6 MS011809-3 MS011809-7 MS011809 iso 1043-1 DIN 6120 sae j1344 j1344 w28c iso 1043-1 polypropylene bga Shipping Trays MEC34 BGA OUTLINE DRAWING TSOP package tray

    VCX16722

    Abstract: No abstract text available
    Text: Revised November 2000 74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16722 low voltage 22-bit register contains twentytwo non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The design


    Original
    PDF 74VCX16722 22-Bit VCX16722

    VCX16722

    Abstract: 74VCX16722 74VCX16722MTD MTD64
    Text: Revised March 1999 74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16722 low voltage 22-bit register contains twentytwo non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The design


    Original
    PDF 74VCX16722 22-Bit VCX16722 74VCX16722 74VCX16722MTD MTD64

    VCX16722

    Abstract: No abstract text available
    Text: Revised April 1999 S E M I C O N D U C T O R TM 74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs General Description Features T h e V C X 1 6722 low voltage 22-bit register contains tw entytw o non-inverting D -type flip-flops w ith 3-STATE outputs


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    PDF 74VCX16722 22-Bit X16722 VCX16722

    GTLP16T1655

    Abstract: GTLP16T1655MTD MTD64
    Text: Prelim inary Revised January 1999 E M IC O N D U C T G R T M GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver Preliminary General Description Features T he G T LP 16T1655 is a 16-bit universal bus transceiver th a t provides LVTTL to G TLP signal level translation. It


    OCR Scan
    PDF GTLP16T1655 16-Bit GTLP16T1655 GTLP16T1655MTD MTD64

    Untitled

    Abstract: No abstract text available
    Text: Preliminary SEM I CONDUCTOR TM GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver Preliminary General Description Features The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data


    OCR Scan
    PDF GTLP16T1655 16-Bit GTLP16T1655

    Untitled

    Abstract: No abstract text available
    Text: Prelim inary Revised January 1999 S E M I C O N D U C T O R TM Features • Bidirectional interface between GTLP and LVTTL logic levels Fairchild’s GTLP has internal edge-rate control and is pro­ cess, voltage, and temperature PVT compensated. Its function is similar to BTL and GTL but with different output


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    PDF GTLP16T1655 GTLP16T1655 16-Bit

    Untitled

    Abstract: No abstract text available
    Text: Prelim inary Revised S eptem ber 1998 S E M I C O N D U C T O R TM GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver Preliminary Features • Bidirectional interface between GTLP and LVTTL logic levels Fairchild's GTLP has internal edge-rate control and is pro­


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    PDF GTLP16T1655 16-Bit TLP16T1655

    VCX16722

    Abstract: 74VCX16722 74VCX16722MTD MTD64
    Text: S E M ¡ C O N D U C T O R p ebm7 J 9 R e v is e d A p rii 1999 TM General Description Features T h e V C X 1 6 7 2 2 lo w v o lta g e 2 2 -b it re g is te r c o n ta in s tw e n ty - • 1 .6 5 V - 3 .6 V V q q s p e c ific a tio n s p ro v id e d tw o n o n -in v e rtin g D -ty p e flip -flo p s w ith 3 -S T A T E o u tp u ts


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    PDF VCX16722 22-Bit VCX16722 74VCX16722 74VCX16722MTD MTD64