I-CUBE iq
Abstract: icube
Text: Company contact: John Bergen I-Cube, Inc. Tel: +1 408 341 1888 Email: john.bergen@icube.com Agency contact: Peter van der Sluijs Neesham Public Relations Tel: +44 0 1442 879222 Email: [email protected] FOR IMMEDIATE RELEASE New I-Cube sales and marketing operations in
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i0802ic
I-CUBE iq
icube
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I-CUBE
Abstract: OCX256
Text: Technical Note OCX256 Layout Guidelines 1.0 Introduction The OCX256 is packaged in a 792-ball plastic TBGA package, and is an SRAM-based bit-oriented switching device offering flow-through NRZ datarates of 667Mb/s and registered data modes of 333MHz. The 128 Inputs and 128 Outputs are each configured as dedicated differential ports. The
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OCX256
792-ball
667Mb/s
333MHz.
I-CUBE
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Controller System NIC
Abstract: 1000base-fx LS125 ls1000 I-CUBE MKT-LS1000-MDS LS120 LS202 "network interface controller"
Text: LS1000 Mini Data Sheet Gigabit Ethernet Port Controller Description Features The LS1000 is a single port interface for 1 Gbit Ethernet switching. It integrates memory control, buffer management, and address translation logic. When combined with an I-Cube Switching Element
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LS1000
LS201
27-Port
LS211
49-Port
MKT-LS1000-MDS
Controller System NIC
1000base-fx
LS125
I-CUBE
MKT-LS1000-MDS
LS120
LS202
"network interface controller"
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i3 processor
Abstract: pin diagram i3 processor block diagram i3 processor iomega Initio I-CUBE INIC-850
Text: initio INIC-850 PCI/CardBus to UltraSCSI Controller Chip Overview The INIC-850 controller chip incorporates all the functionality of a high-performance UltraSCSI host adapter in a single chip solution. Suited for CardBus, motherboards and addon host adapter cards, the INIC-850 supports a wide range
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INIC-850
INIC-850
D155-01
i3 processor
pin diagram i3 processor
block diagram i3 processor
iomega
Initio
I-CUBE
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I-CUBE
Abstract: DRAM Controller FPGA Schematics 16 M 512kx8 dram simm BITBLASTER DRAM Controller FPGA Schematics 79RV4640 7M9510 IDT79RV4640 IDT7M9510 IEEE1386
Text: PRELIMINARY IDT7M9510 IDT79RV4640 CPU-BASED PCI MEZZANINE CARD Integrated Device Technology, Inc. FEATURES: • Other Features – Manual Cold Reset Pushbutton and two pin header – hardware based masking of interrupts – Configurable Timer Interrupt Generator
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IDT7M9510
IDT79RV4640
IEEE1386)
100MHz,
150Mhz,
180MHz
50MHz
33MHz
72-position
I-CUBE
DRAM Controller FPGA Schematics 16 M
512kx8 dram simm
BITBLASTER
DRAM Controller FPGA Schematics
79RV4640
7M9510
IDT7M9510
IEEE1386
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OCX1601
Abstract: "differential input" common mode voltage LVDS OCX160 V1689 V1406
Text: Application Brief Operating the OCX1601 in LVDS Applications 1.0 Introduction The OCX1601 is the second member of I-Cube’s OCX family of devices to have integrated termination and attenuation resistors, whereas earlier designs of the OCX device i.e. OCX160 required external resistors to
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OCX1601
OCX160)
OCX160
OCX1601,
OCX961
OCX4815710550,
"differential input" common mode voltage LVDS
V1689
V1406
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Untitled
Abstract: No abstract text available
Text: PSX Family Data Sheet FEATURES DESCRIPTION • SRAM-based, in-system programmable • Switch Matrix — Non-Blocking — Programmable Bus Widths of 4, 8, 16 and 32 bits — Identical and Predictable Delays — One-to-One, One-to-Many and Many-to-One Connections
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133MHz
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Untitled
Abstract: No abstract text available
Text: OCX961 Crosspoint Switch Advanced Mini Data Sheet Features • • • • 1.6 Gb/s port data bandwidth, >77Gb/s aggregate bandwidth Low power CMOS, 2.5V and 3.3V power supply SRAM-based, in-system programmable 96 configurable I/O ports – 48 dedicated differential input ports
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OCX961
77Gb/s
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N38 transistor
Abstract: w38 transistor AR33 crosspoint 256 x 256 ocx 256 E23 transistor AB-39
Text: OCX256 Crosspoint Switch Advanced Data Sheet Features • • • • 667 Mb/s port data bandwidth, >85Gb/s aggregate bandwidth Low power CMOS, 2.5V and 3.3V power supply SRAM-based, in-system programmable 256 configurable I/O ports – 128 dedicated differential input ports
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OCX256
85Gb/s
all2593,
MKT-OCX256-DS
N38 transistor
w38 transistor
AR33
crosspoint 256 x 256 ocx 256
E23 transistor
AB-39
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P132-P134
Abstract: p331 TRANSISTOR P452
Text: MSX Family Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor
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aw7 TRANSISTOR
Abstract: P449 I-CUBE iq P-033 Bus repeater p426 P-238 P122-P120 p331 TRANSISTOR P339
Text: MSX Family Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor
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Untitled
Abstract: No abstract text available
Text: OCX256 Crosspoint Switch Advanced Data Sheet Features • • • • 667 Mb/s port data bandwidth, >85Gb/s aggregate bandwidth Low power CMOS, 2.5V and 3.3V power supply SRAM-based, in-system programmable LVDS I/O OCX256L and LVPECL I/O (OCX256P) versions
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OCX256
85Gb/s
OCX256L)
OCX256P)
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Scan AV6
Abstract: No abstract text available
Text: OCX256 Crosspoint Switch Advanced Data Sheet Features • • • • 667 Mb/s port data bandwidth, >85Gb/s aggregate bandwidth Low power CMOS, 2.5V and 3.3V power supply SRAM-based, in-system programmable LVDS I/O OCX256L and LVPECL I/O (OCX256P) versions
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OCX256
85Gb/s
OCX256L)
OCX256P)
Scan AV6
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Untitled
Abstract: No abstract text available
Text: IQX Family Data Sheet FEATURES DESCRIPTION • SRAM-based, in-system programmable • Switch Matrix — Non-Blocking — Identical and predictable delays — One-to-one, one-to-many and many-to-one connections The IQX family of SRAM-based bit-oriented switching devices is
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power5465056,
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JTAG MINI
Abstract: Bus repeater
Text: MSX Family Mini Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor
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I-CUBE
Abstract: P005 p055 TRANSISTOR IDS200 p055 power transistor IQ32B IQ48 IQ64B IQ96 84l transistor
Text: I-Cube IQ Family Data Sheet m F eatures D e s c r ip t io n • SRAM-based, in-system programmable The IQ family of SRAM-based bit-oriented switching devices is • Switch Matrix manufactured using 0.6|jm CMOS processes. These devices — Non-Blocking offer clock speeds of up to 150 MHz and pin-to-pin delay as low
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IQ32B-TQ52
IQ64B
IQ32B
144PQ
100TQ
144TQ
I-CUBE
P005
p055 TRANSISTOR
IDS200
p055 power transistor
IQ32B
IQ48
IQ96
84l transistor
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IQ160
Abstract: IDS200 TLR 308 IQ128B IQ240B IQ320 IQ32B IQ48 IQ64B IQ96
Text: Introduction This manual describes the architecture o f the IQ family of integrated circuit chips, which includes the IQ320, IQ240B, IQ160, IQ128B, IQ96, IQ64B, IQ48, and IQ32B part types. Each IQ device implements a non-blocking switch matrix. Each signal line in
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IQ320,
IQ240B,
IQ160,
IQ128B,
IQ64B,
IQ32B
TQG41Ã
IQ64B
IQ32B
IQ160
IDS200
TLR 308
IQ128B
IQ240B
IQ320
IQ48
IQ64B
IQ96
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Untitled
Abstract: No abstract text available
Text: Introduction This manual provides the information needed to configure the PSX Family devices using the JTAG interface. It is intended for users who plan to write their own code to configure the PSX devices. In addition, this manual explains how the boundary scan features implemented in the PSX devices can be used
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PSX160,
PSX128B
PSX96B.
has27
DDD11SG
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Untitled
Abstract: No abstract text available
Text: LS125 Data Sheet I-Cube SATC Controller Description Features 33 M Hz 32-bit PCI bus interface, 8 interrapt lines to support up to 8 LS port controllers. 32 or 48 bit Interface with standard asynchronous SRAM to internal port map registers cache up to 128K MAC addresses.
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LS125
32-bit
125-DS
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Untitled
Abstract: No abstract text available
Text: LS211 ' * - I-Cube* 49 Port LAN Switching Element D escription Features • Single chip, Fast Ethernet switching fabric • Up to 100 M bit per-port switching capacity • Supports 49 full duplex ports • Four dedicated programmable output ports for M ulticast, port mirroring, or other port usage
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LS211
LS211
PQ256
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asx340
Abstract: je 243 PLK3210 109-149 IQX160 JE 33 IQX128B IQX240B IQX320 se 336
Text: Introduction T his m anual provides the inform ation needed to configure th e IQ X Fam ily devices using the JT A G interface. It is in ten d ed fo r u sers w ho p lan to w rite th eir ow n code to configure the IQ X devices. In addition, this m anual explains
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I-CUBE
Abstract: P103t zener diode phc 16 ZENER diode p317 AB P89 zener PLK3210 hk30 transistor 4287 AB zener phc 12 kck 223
Text: SH5 I-Cube* IQX Family Data Sheet Description Features The IQX family of SRAM-based bit-oriented switching devices is manufactured using a 0.6vim CMOS process. These devices offer clock speed of up to 150 MHz and fastest pin-to-pin delay of 6 ns. • SRAM-based, in-system programmable
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D-11-014W
I-CUBE
P103t
zener diode phc 16
ZENER diode p317
AB P89 zener
PLK3210
hk30
transistor 4287 AB
zener phc 12
kck 223
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RJP 3045
Abstract: Transistor z3p NP02 P104t str 1195 P022J I-CUBE iq P116C RP011 7805 v5
Text: M Ä ' I- C IQ Family Data Sheet u b e Features Description • Eight d evices ran gin g from 32 to 320 I / O Ports The IQ d evices are designed for use in sw itching and interconnect applications. In sw itching applications, these d evices are used to d ynam ically sw itch one or m ore signals. W hen
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2328-C
RJP 3045
Transistor z3p
NP02
P104t
str 1195
P022J
I-CUBE iq
P116C
RP011
7805 v5
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Untitled
Abstract: No abstract text available
Text: I-Cube’ LSlOO Quad-Port Ethernet Switch Interface & Features Description • Integrated PCI bus interface for port management • Integrated memory controller and buffer manager • Integrated 64 entry address translation cache • Integrated port statistics collection
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LS101
LS100
PQ256
BG256
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