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    Text: May.7 ‘93 MITSUBISHI LSIs M5M4V16407ATP-10,-12,-15 Preliminary 16M 4194304 - WORD BY 4 - BIT Synchronous DRAM PRELIMINARY This document is a preliminary specification and some of the contents are sub­ ject to change without notice. DESCRIPTION The M5M4V16407A incorporates 8 bit data registers and amultiplexer into a 4194304-word by 4-bit


    OCR Scan     		PDF M5M4V16407ATP-10 M5M4V16407A 4194304-word A0-10 DD27bbb G027bb7