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    CY7C1347 Price and Stock

    Rochester Electronics LLC CY7C1347D-166AC

    IC SRAM 4.5MBIT PAR 100TQFP
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    DigiKey CY7C1347D-166AC Bulk 50
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    Flip Electronics CY7C1347G-250AXC

    IC SRAM 4.5MBIT PAR 100TQFP
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    DigiKey CY7C1347G-250AXC Tray 150
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    Rochester Electronics LLC CY7C1347G-250AXC

    CACHE SRAM, 128KX36, 2.6NS PQFP1
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    DigiKey CY7C1347G-250AXC Tray 49
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    Infineon Technologies AG CY7C1347G-250AXC

    IC SRAM 4.5MBIT PAR 100TQFP
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    Avnet Americas CY7C1347G-250AXC Tray 0 Weeks, 2 Days 177
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    Infineon Technologies AG CY7C1347S-166BGC

    IC SRAM 4.5MBIT PAR 119PBGA
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    DigiKey CY7C1347S-166BGC Tray 840
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    Find more CY7C1347 price and stock on Findchips.com

    CY7C1347 Datasheets (74)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1347 Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347-100AC Cypress Semiconductor Cache Memory Original PDF
    CY7C1347-100AC Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347-100AI Cypress Semiconductor Cache Memory Original PDF
    CY7C1347-117AC Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347-133AC Cypress Semiconductor Cache Memory Original PDF
    CY7C1347-133AC Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347-166AC Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347A Cypress Semiconductor 128K x 36 Synchronous Pipelined Burst SRAM Original PDF
    CY7C1347B Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347B-100AC Cypress Semiconductor IC SRAM 4.5MBIT 100MHZ 100LQFP Original PDF
    CY7C1347B-133AC Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347B-166AC Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347B-166BGC Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347C Cypress Semiconductor 256K x 18/128K x 36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347C-166BGC Cypress Semiconductor Cache Memory, 256K x 18/128Kx36 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1347C-166BGCT Cypress Semiconductor Cache Memory, 256K x 18/128Kx36 Synchronous-Pipelined Cache RAM, Tape and Reel Original PDF
    CY7C1347D Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache SRAM Original PDF
    CY7C1347D-166AC Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache SRAM Original PDF
    CY7C1347D-200AC Cypress Semiconductor 128K x 36 Synchronous-Pipelined Cache SRAM Original PDF

    CY7C1347 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)


    Original     		PDF CY7C1347G CY7C1347G

    CY7C1347B

    Abstract: memory depth expansion
    Text: CY7C1347 CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Supports 100-MHz bus for Pentium  and PowerPC operations with zero wait states


    Original     		PDF 1CY7C1347 CY7C1347B CY7C1347B 100-MHz 166-MHz memory depth expansion

    CY7C1347D

    Abstract: CY7C1347D-225BGC CY7C1347D-250AC CY7C1347D-250BGC
    Text: 327 CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features • • • • • • • • • • • • • • • • • • • Fast access times: 2.5 and 3.5 ns Fast clock speed: 250, 225, 200, and 166 MHz 1.5 ns set-up time and 0.5 ns hold time


    Original     		PDF CY7C1347D CY7C1347D: CY7C1347D CY7C1347D-225BGC CY7C1347D-250AC CY7C1347D-250BGC

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)


    Original     		PDF CY7C1347G 100-pin 119-ball

    CY7C1347G-133AXI

    Abstract: CY7C1347G-166BGC CY7C1347G CY7C1347G-200AXC CY7C1347G-200BGC CY7C1347G-225AXC CY7C1347G-250AXC CY7C1347G-250BGC
    Text: PRELIMINARY CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times


    Original     		PDF CY7C1347G 250-MHz 225-MHz 200-MHz 166-MHz 133-MHz 100-MHz 100-pin 119-pin 165-pin CY7C1347G-133AXI CY7C1347G-166BGC CY7C1347G CY7C1347G-200AXC CY7C1347G-200BGC CY7C1347G-225AXC CY7C1347G-250AXC CY7C1347G-250BGC

    CY7C1347F

    Abstract: CY7C1347F-200AC CY7C1347F-225AC CY7C1347F-225BGC CY7C1347F-250AC CY7C1347F-250BGC
    Text: CY7C1347F 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache


    Original     		PDF CY7C1347F CY7C1347F 119-Ball CY7C1347F-200AC CY7C1347F-225AC CY7C1347F-225BGC CY7C1347F-250AC CY7C1347F-250BGC

    CY7C1347

    Abstract: No abstract text available
    Text: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states


    Original     		PDF CY7C1347 CY7C1347 100-MHz 166-MHz 133-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)


    Original     		PDF CY7C1347G 100-pin 119-ball

    CY7C1347D-250BGC

    Abstract: CY7C1347D CY7C1347D-225BGC CY7C1347D-250AC
    Text: 327 CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features • • • • • • • • • • • • • • • • • • • Fast access times: 2.5 and 3.5 ns Fast clock speed: 250, 225, 200, and 166 MHz 1.5 ns set-up time and 0.5 ns hold time


    Original     		PDF CY7C1347D CY7C1347D: BG119) CY7C1347D-250BGC CY7C1347D CY7C1347D-225BGC CY7C1347D-250AC

    CY7C1347B

    Abstract: No abstract text available
    Text: CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states


    Original     		PDF CY7C1347B CY7C1347B 100-MHz 166-MHz 166-MHz

    CY7C1347

    Abstract: No abstract text available
    Text: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states


    Original     		PDF CY7C1347 CY7C1347 100-MHz 166-MHz 133-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features Functional Description • Fast access times: 2.5 and 3.5 ns This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell


    Original     		PDF CY7C1347D CY7C1347D: BG119) 166BGA, 200BGA, 225AC

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states


    Original     		PDF CY7C1347B 100-MHz 166-MHz 133-MHz

    165 ball

    Abstract: CY7C1347G-133AXI AN1064 CY7C1347G
    Text: CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • • • • • The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at


    Original     		PDF CY7C1347G CY7C1347G 165 ball CY7C1347G-133AXI AN1064

    CY7C1347F

    Abstract: CY7C1347F-166BGI
    Text: CY7C1347F 128K x 36 Pipelined Sync SRAM Features CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture


    Original     		PDF CY7C1347F CY7C1347F 250-MHz 225-MHz 200-MHz 166-MHz 133-MHz 100-MHz CY7C1347F-166BGI

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Functional Description Features • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)


    Original     		PDF CY7C1347G 100-pin 119-ball

    CY7C1347

    Abstract: CY7C1347-133AC
    Text: fax id: 1113 PRELIMINARY CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1347 is a 3.3V 128K by 36 synchronous-pipelined cache SRAM designed to support zero wait state secondary


    Original     		PDF CY7C1347 CY7C1347 100-MHz 166-MHz CY7C1347-133AC

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)


    Original     		PDF CY7C1347G CY7C1347G

    CY7C1347F

    Abstract: No abstract text available
    Text: 347F PRELIMINARY CY7C1347F 128K x 36 Pipelined Sync SRAM Features CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture


    Original     		PDF CY7C1347F 250-MHz 225-MHz 200-MHz 166-MHz 133-MHz 100-MHz 100-pin 119-pin 165-pin CY7C1347F

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K x 36 common I/O architecture • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ)


    Original     		PDF CY7C1347G 250-MHz 100-Pin 119-Ball 165-Ball

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states


    Original     		PDF CY7C1347 100-MHz 166-MHz 133-MHz CY7C1347

    AN1064

    Abstract: CY7C1347G
    Text: CY7C1347G 4 Mbit 128K x 36 Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for Pipelined Operation ■ 128K x 36 common I/O architecture ■ 3.3V core Power Supply (VDD) ■ 2.5V/3.3V I/O Power Supply (VDDQ) ■


    Original     		PDF CY7C1347G 100-Pin 119-Ball 165-Ball AN1064 CY7C1347G

    CY7C1347

    Abstract: CY7C1347-166AC
    Text: CY7C1347 V CYPRESS 128K X 36 Synchronous-Pipelined Cache RAM T he CY7C1347 I/O pins can operate at eith e r the 2.5V or the 3.3V level, the I/O pins are 3.3V to le ra n t w h en V ddq =2.5V. Features • S u p p o rts 1 0 0-M H z bus fo r Pentium o p e ratio n s w ith zero w ait sta tes


    OCR Scan     		PDF CY7C1347 100-MHz 166-MHz 133-MHz CY7C1347 CY7C1347-166AC

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V DDQ=2.5V. • Supports 1 0O-MHz bus for Pentium and PowerPC operations with zero wait states


    OCR Scan     		PDF CY7C1347 166-MHz 133-MHz 100-MHz CY7C1347