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    CPLD Search Results

    CPLD Result Highlights (2)

    Part ECAD Model Manufacturer Description Download Buy
    JM38510/50407BRA Texas Instruments Standard High-Speed PAL Circuits 20-CDIP -55 to 125 Visit Texas Instruments Buy
    JM38510/50402BRA Texas Instruments Standard High-Speed PAL Circuits 20-CDIP -55 to 125 Visit Texas Instruments Buy
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    CPLD Price and Stock

    Microchip Technology Inc TPDCPLD1

    KIT DEVELOPMENT CPLD BARTEK
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    AMD DO-CPLD-DK

    STARTER KIT CPLD
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    AMD DO-CPLD-DK-J

    KIT STARTER CPLD-JAPANESE
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    Phyton Inc CPI2-D-MCPLD

    MICROCHIP PLD DEVICE LIBRARY
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    AMD DO-CPLD-DK-G

    KIT DESIGN CPLD W/BATT HOLDER
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    CPLD Datasheets (6)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CPLD-2 22V10 s in 24-pin Package Atmel ATF750C(L) , 20 FFs, 10 I-O Pins, standard & low power Original PDF
    CPLD-2 22V10 s in 24-pin Package Atmel ATF750LVC , 20 FFs, 10 I-O Pins, 3-volt & 3-volt low power Original PDF
    CPLD ATF15xx Family-Industry Compatible Atmel ATF1500A (L) , 1500 gate electrically erasable CPLD, 44 pins Original PDF
    CPLD ATF15xx Family-Industry Compatible Atmel ATF1516AS(L) , 256 Macrocell, standard & low power w-ISP Original PDF
    CPLD ATF15xx Family-Industry Compatible Atmel ATF1508ASV(L) , 128 Macrcells with ISP, 3-volt and low power Original PDF
    CPLD-Proprietary Atmel ATV2500B (BQ)(BQL) , 2500 gate high-speed CPLD, standard & low power, 40 & 44 pins Original PDF

    CPLD Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    SW-QUARTUS-SE-FIX

    Abstract: No abstract text available
    Text: Quartus II Design Software Fast Path to Your Design Quartus II software is #1 in performance and productivity for CPLD, FPGA, and ASIC designs, providing the fastest path to convert your concept into reality. Quartus II Key Features Faster Compile Time Incremental


    Original     		PDF GB-1001-1 SW-QUARTUS-SE-FIX

    cypress flash 370

    Abstract: logic block diagram of cypress flash 370 device 22v10 CY7C375 FLASH370 o112i cypress flash 370 CPLD cypress flash 370 device technology
    Text: fax id: 6130 For new designs see CY7C375i CY7C375 UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 28 macrocells in eight logic blocks • 28 I/O pins • 6 dedicated inputs including 4 clock pins • Bus Hold capabilities on all I/Os and dedicated inputs


    Original     		PDF CY7C375i CY7C375 128-Macrocell CY7C375 LASH370TM FLASH370 22V10 I/O112-I/O127 cypress flash 370 logic block diagram of cypress flash 370 device o112i cypress flash 370 CPLD cypress flash 370 device technology

    XC9572

    Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
    Text: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable


    Original     		PDF XC9572 DS065 36V18 XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C

    XCR3128XL-10VQ100I

    Abstract: XCR3128XL-10TQ144I XCR3128XL-7CS144I XCR3128XL XCR3128XL-10CS144I XCR3128XL-10VQ100C CS144 marking E13 diode L12M1 k3296
    Text: R XCR3128XL 128 Macrocell CPLD DS016 v2.1 August 21, 2003 14 Preliminary Product Specification Features Description • Low power 3.3V 128 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 175 MHz • 128 macrocells with 3,000 usable gates


    Original     		PDF XCR3128XL DS016 144-pin 144-ball 100-pin XCR3128XL-10VQ100I XCR3128XL-10TQ144I XCR3128XL-7CS144I XCR3128XL-10CS144I XCR3128XL-10VQ100C CS144 marking E13 diode L12M1 k3296

    XCR5128

    Abstract: MC16 XCR3128 Xilinx XCR5128 P-QFP40
    Text: APPLICATION NOTE This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. R DS041 v1.4 January 19, 2001 XCR5128: 128 Macrocell CPLD 14* Product Specification Features Description • The XCR5128 CPLD (Complex Programmable Logic


    Original     		PDF com/partinfo/notify/pdn0007 DS041 XCR5128: XCR5128 100-pin VQ100: TQ128: 128-pin MC16 XCR3128 Xilinx XCR5128 P-QFP40

    EPC1213PC8

    Abstract: EPC1PC8 EPC2LC20 epc2tc32 EPC4QC100 EPM7128* kit NIOS-EVALKIT-1C12 EPC1441PC8 EPC16UC88 EPM1270F256C5ES
    Text: NEW! Package 100-TQFP 100-TQFP 100-TQFP 44-TQFP 44-TQFP 44-TQFP 44-TQFP 84-PLCC 100-TQFP 100-TQFP 100-TQFP 144-TQFP 100-TQFP 100-TQFP 144-TQFP * Tube CPLD’s Cont. Macro Cells Logic Elements Pin-Pin Delay (ns) I/O Pins Voltage Speed (NS) 64 64 64 64 64


    Original     		PDF 100-TQFP 44-TQFP 84-PLCC EPC1213PC8 EPC1PC8 EPC2LC20 epc2tc32 EPC4QC100 EPM7128* kit NIOS-EVALKIT-1C12 EPC1441PC8 EPC16UC88 EPM1270F256C5ES

    Untitled

    Abstract: No abstract text available
    Text: CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins


    Original     		PDF CY7C371i 32-Macrocell 22V10, FLASH370i

    XC95144XL-10TQ144I

    Abstract: XC95144XL-10TQG100C XAPP114 XAPP427 XC9500XL XC95144 XC95144XL XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144
    Text: XC95144XL High Performance CPLD R DS056 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC95144XL DS056 XC9500XL CS144 220oC. XC95144XL-10TQ144I XC95144XL-10TQG100C XAPP114 XAPP427 XC95144 XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144

    Untitled

    Abstract: No abstract text available
    Text: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – k XC9500 In-System Programmable CPLD Family R DS063 v6.0 May 17, 2013 Product Specification Features - Advanced CMOS 5V FastFLASH technology • - Supports parallel programming of multiple XC9500 devices High-performance


    Original     		PDF XC9500 DS063 XC9500 36V18 produ2/10/1999 XC95288. 352-pin XC95216. XCN07010 XCN11010

    020000040000FA

    Abstract: AT17LV AT17LV002 AT17LV010 AT17LV512 CY3LV010 CY3LV512 CYDH2200E Cypress CY39100V208B processor RECONFIG
    Text: Configuring Delta39K /Quantum38K™ CPLDs Overview This application note discusses the configuration interfaces, modes, and processes of the Delta39K™ and Quantum38K™ CPLDs and includes examples of device set-up. Each member of the Delta39K family is available in volatile


    Original     		PDF Delta39KTM/Quantum38KTM Delta39KTM Quantum38KTM Delta39K 020000040000FA AT17LV AT17LV002 AT17LV010 AT17LV512 CY3LV010 CY3LV512 CYDH2200E Cypress CY39100V208B processor RECONFIG

    PLCC-48 footprint

    Abstract: XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 XC9500 XC9500 pinout
    Text: XC9500 In-System Programmable CPLD Family R December 14, 1998 Version 3.0 1* Features Family Overview • The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system


    Original     		PDF XC9500 PLCC-48 footprint XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 XC9500 pinout

    GR2286

    Abstract: GR2284i 100N XC2064 XC3090 XC4005 XC5210 XC9500 SVF Series GR2281i
    Text: Programming Xilinx XC9500 CPLDs on GENRAD Testers Preface JTAG Programmer Version Creating GenRad Test Files Table of Contents Introduction Creating SVF Files Revision 1.3 November 20, 1998 Printed in U.S.A. svf2dts Conversion Utility R The Xilinx logo shown above is a registered trademark of Xilinx, Inc.


    Original     		PDF XC9500 XC2064, XC3090, XC4005, XC5210, XC-DS501, XC9500 GR2286 GR2284i 100N XC2064 XC3090 XC4005 XC5210 SVF Series GR2281i

    AN070

    Abstract: philips application manchester manchester code verilog manchester verilog decoder manchester encoder an070
    Text: INTEGRATED CIRCUITS AN070 Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs 1997 May 14 Philips Semiconductors Philips Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs AN070 In this application note, Manchester code is defined, and the


    Original     		PDF AN070 AN070 philips application manchester manchester code verilog manchester verilog decoder manchester encoder an070

    2128E

    Abstract: isplsi2 signal path designer
    Text: PCI Bus Target Controller Implementation Using a Lattice ispLSI CPLD and the relevant electrical and timing characteristics are discussed. The Lattice Semiconductor Data Book or CDROM and the PCI Specification should be consulted to obtain more detailed information.


    Original     		PDF

    PZ3032DS10

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS PZ3032A/PZ3032D 32 macrocell CPLD with enhanced clocking Preliminary specification IC27 Data Handbook Philips Semiconductors 1998 Jul 20 Philips Semiconductors Preliminary specification 32 macrocell CPLD with enhanced clocking FEATURES


    Original     		PDF PZ3032A/PZ3032D PZ3032A/PZ3032D PZ3032DS10

    pz5064c

    Abstract: PZ5064C10BC PZ5064C7A44 PZ5064C7BC PZ5064N10A44 PZ5064N10BC PZ5064N12A44 PZ5064N12BC PZ5064C10A44
    Text: INTEGRATED CIRCUITS PZ5064C/PZ5064N 64 macrocell CPLD with enhanced clocking Preliminary specification Supersedes data of 1998 May 05 IC27 Data Handbook Philips Semiconductors 1998 Jul 21 Philips Semiconductors Preliminary specification 64 macrocell CPLD with enhanced clocking


    Original     		PDF PZ5064C/PZ5064N PZ5064C/PZ5064N 50MHz pz5064c PZ5064C10BC PZ5064C7A44 PZ5064C7BC PZ5064N10A44 PZ5064N10BC PZ5064N12A44 PZ5064N12BC PZ5064C10A44

    XC9500

    Abstract: XC95108 GSR 10,8
    Text: 1 XC95108 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins


    Original     		PDF XC95108 36V18 84-Pin 100-Pin 160-Pin XC95108 PQ100 TQ100 PQ160 XC9500 GSR 10,8

    XAPP393

    Abstract: DS090 VQ100 XC2C128 XC2C256 XC2C32 XC2C384 XC2C64 interfacing 8051 XC9500 cpld pins table
    Text: R CoolRunner-II CPLD Family DS090 v1.7 October 2, 2003 Preliminary Product Specification Features • • • • Optimized for 1.8V systems - Industry’s fastest low power CPLD - Static Icc of less than 100 microamps at all times - Densities from 32 to 512 macrocells


    Original     		PDF DS090 IEEE1149 f/wp170 XAPP393 DS090 VQ100 XC2C128 XC2C256 XC2C32 XC2C384 XC2C64 interfacing 8051 XC9500 cpld pins table

    CY7C373

    Abstract: CY7C374 FLASH370
    Text: For new designs see CY7C373i CY7C373 UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks The CY7C373 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the FLASH370TM family of


    Original     		PDF CY7C373i CY7C373 64-Macrocell CY7C373 FLASH370TM FLASH370 22V10 I/O16-I/O31 CY7C374

    cy37128

    Abstract: CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700
    Text: = m m m !Æ '^ r ^ r : c Q CY3 7 1 2 8 PR £um A ^Y UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.0 ns Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming


    OCR Scan     		PDF CY37128 128-Macrocell cy37128 CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700

    84 PIN CERAMIC QUAD FLAT PACK

    Abstract: 2600 corning cypress flash 370 7C374-100 7C374-66 7C374L-66 CY7C373 CY7C374 FLASH370 CY7C374-83GC
    Text: fax id: 6129 —— — - = : ! W Æ j r I 1 CY7C374 17 Q Q IT C O O UltraLogic 128-Macrocell Flash CPLD Features The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource— the Programmable Interconnect Matrix PIM . The PIM brings flex­


    OCR Scan     		PDF CY7C374 128-Macrocell 84-pin 100-pin CY7C373 CY7C374 ASH370t FLASH370 84 PIN CERAMIC QUAD FLAT PACK 2600 corning cypress flash 370 7C374-100 7C374-66 7C374L-66 CY7C374-83GC

    CY37384

    Abstract: CY37384V L0651
    Text: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.


    OCR Scan     		PDF CY37384V 384-Macrocell CY37384 CY37384V L0651

    Ultra37064

    Abstract: CERAMIC LEADLESS CHIP CARRIER CY7C372 CY7C373 ieee1149.1 cypress
    Text: J ^ m n rn n : if : Y PRELIMINARY H Ultra37064 - UltraLogic 64-Macrocell ISR™ CPLD Features — ts = 3.5 ns — tc o = 4.5 ns • 64 m a cro cells in fo u r logic blocks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™


    OCR Scan     		PDF Ultra37064 64-Macrocell 167MHz IEEE1149 Ultra37064 CERAMIC LEADLESS CHIP CARRIER CY7C372 CY7C373 ieee1149.1 cypress

    MX 0541

    Abstract: mx 0541 b CY7C373
    Text: fax id: 6138 CY7C373Ì CYPRESS UltraLogic 64-Macrocell Flash CPLD Functional Description Features • 64 m a cro cells in fo u r logic blocks The C Y 7 C 3 73i is an In-System R eprogram m able C om plex P rogram m able Logic Device CPLD and is pa rt of the


    OCR Scan     		PDF CY7C373Ã 64-Macrocell 84-pin 100-pin CY7C374i CY7C373i FLASH370iâ MX 0541 mx 0541 b CY7C373