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    A3P015 Search Results

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    A3P015 Price and Stock

    Microchip Technology Inc A3P015-QNG68

    IC FPGA 49 I/O 68QFN
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    Microchip Technology Inc A3P015-2QNG68

    IC FPGA 49 I/O 68QFN
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    Microchip Technology Inc A3P015-1QNG68

    IC FPGA 49 I/O 68QFN
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    Microchip Technology Inc A3P015-QNG68I

    IC FPGA 49 I/O 68QFN
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    DigiKey A3P015-QNG68I Tray 260
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    Microchip Technology Inc A3P015-1QNG68I

    IC FPGA 49 I/O 68QFN
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    DigiKey A3P015-1QNG68I Tray 260
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    A3P015 Datasheets (7)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    A3P015-1QNG68 Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 49 I/O 68QFN Original PDF
    A3P015-1QNG68I Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 49 I/O 68QFN Original PDF
    A3P015-2QNG68 Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 49 I/O 68QFN Original PDF
    A3P015-2QNG68I Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 49 I/O 68QFN Original PDF
    A3P015-QNG68 Actel ProASIC3 Flash FPGA 15K System Gates Original PDF
    A3P015-QNG68 Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 49 I/O 68QFN Original PDF
    A3P015-QNG68I Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 49 I/O 68QFN Original PDF

    A3P015 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: Revision 15 ProASIC3 Flash Family FPGAs with Optional Soft ARM Support Features and Benefits Advanced I/O High Capacity • 15 K to 1 M System Gates • Up to 144 Kbits of True Dual-Port SRAM • Up to 300 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS


    Original
    PDF 130-nm, 64-Bit 128-Bit

    peak china qfn 9 x 9 tray drawing

    Abstract: semi catalog AGL1000-FG484
    Text: IGLOO Handbook IGLOO Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO Datasheet IGLOO Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I


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    connect usb in vcd player circuit diagram

    Abstract: DIODE MARKING 534
    Text: IGLOOe Handbook IGLOOe Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOOe Datasheet IGLOOe Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I


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    Untitled

    Abstract: No abstract text available
    Text: 2 – ProASIC3 DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA


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    verilog code for 128 bit AES encryption

    Abstract: 4 bit bistable latch vhdl code zoom 505 schematic 0.13-um CMOS standard cell library inverter
    Text: Automotive ProASIC 3 Handbook Automotive ProASIC3 Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – Automotive ProASIC3 Datasheet Automotive ProASIC3 Flash Family FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1


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    Untitled

    Abstract: No abstract text available
    Text: IGLOO nano Handbook IGLOO nano Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO nano Datasheet IGLOO nano Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I


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    IO191

    Abstract: vhdl code for fifo and transmitter actel FG484 package mechanical drawing
    Text: ProASIC 3L Low-Power Handbook ProASIC3L Low-Power Flash Device Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – ProASICL Low-Power Datasheet


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    PDF

    proasic3e

    Abstract: No abstract text available
    Text: Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Introduction This document outlines the following device information: Clock Conditioning Circuits CCC features, PLL core specifications, functional descriptions, software configuration information,


    Original
    PDF A3P015, AGL015, AGLP030, AGLP060, AGLP125. proasic3e

    Untitled

    Abstract: No abstract text available
    Text: Radiation-Tolerant ProASIC 3 Handbook Radiation-Tolerant ProASIC3 Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – Radiation-Tolerant ProASIC3 FPGAs Datasheet


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    IR 907

    Abstract: No abstract text available
    Text: IGLOO Handbook IGLOO Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO Datasheet IGLOO Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I


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    PS 229

    Abstract: A3P250 A3P400 A3P600 PQ208 QN132 VQ100 cmos switch charge pump A3P100 A3P015
    Text: Revision 10 ProASIC3 Flash Family FPGAs with Optional Soft ARM Support Features and Benefits Advanced I/O High Capacity • 15 k to 1 M System Gates • Up to 144 kbits of True Dual-Port SRAM • Up to 300 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS


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    PDF 130-nm, 64-Bit 128-Bit PS 229 A3P250 A3P400 A3P600 PQ208 QN132 VQ100 cmos switch charge pump A3P100 A3P015

    E1 3007-2

    Abstract: A3P030 A3P060 A3P125 A3P250 A3P400 C8051F120 a3pl
    Text: DirectC v2.4 User’s Guide Actel Corporation, Mountain View, CA 94043 2009 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5-02-00079-5 Release: May 2009 No part of this document may be copied or reproduced in any form or by any means without prior written


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    Untitled

    Abstract: No abstract text available
    Text: Revision 9 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V


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    ACTEL FUSION AFS1500

    Abstract: 50 pin flat ribbon cable DC SERVO MOTOR CONTROL VHDL GF 036 V6 Logic Cross-Reference A54 ZENER AFS600-FG256 AQ3 Series flashpro3 schematic leon3
    Text: Actel Fusion Handbook Low-Power Flash Device Handbooks Introduction Device Handbooks contain all the information available to help designers understand and use Actel's devices. Handbook chapters are grouped into sections on the website to simplify navigation. Each chapter of the handbook can be viewed as an individual PDF file.


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    A3P1000

    Abstract: 160 e7 Datasheet A3P125 FBGA A3P250 A3P030 FBGA A3P600
    Text: ProASIC3 Packaging 3 – Package Pin Assignments 48-Pin QFN Pin 1 48 1 Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground GND . Note For Package Manufacturing and Environmental information, visit the Resource Center at


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    PDF 48-Pin A3P030 IO82RSB1 IO24RSB0 GEC0/IO73RSB1 IO22RSB0 GEA0/IO72RSB1 A3P1000 160 e7 Datasheet A3P125 FBGA A3P250 FBGA A3P600

    A3P060

    Abstract: ProASIC3 A3P250 A3P250 QN68 A3P030 QN132 TQ144 VQ100 ProASIC3 lvds proasic3 a3p125
    Text: v1.3 ProASIC3 Flash Family FPGAs with Optional Soft ARM® Support Features and Benefits High Capacity • 15 k to 1 M System Gates • Up to 144 kbits of True Dual-Port SRAM • Up to 300 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process


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    PDF 130-nm, 64-Bit A3P060 ProASIC3 A3P250 A3P250 QN68 A3P030 QN132 TQ144 VQ100 ProASIC3 lvds proasic3 a3p125

    A3P060

    Abstract: A3P125 A3P400 A3P030 FBGA A3P600 A3P1000
    Text: ProASIC3 Packaging 3 – Package Pin Assignments 48-Pin QFN Pin 1 48 1 Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground GND . Note For Package Manufacturing and Environmental information, visit the Resource Center at


    Original
    PDF 48-Pin A3P030 IO82RSB1 IO24RSB0 GEC0/IO73RSB1 IO22RSB0 GEA0/IO72RSB1 A3P060 A3P125 A3P400 FBGA A3P600 A3P1000

    Untitled

    Abstract: No abstract text available
    Text: Revision 10 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V


    Original
    PDF

    Untitled

    Abstract: No abstract text available
    Text: Revision 11 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V


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    ProASIC3 A3P250

    Abstract: A3P600 A3P030 A3P060 A3P1000 A3P125 A3P250 A3P400 PAC10
    Text: 2 – ProASIC3 DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


    Original
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    Untitled

    Abstract: No abstract text available
    Text: Revision 13 ProASIC3 Flash Family FPGAs with Optional Soft ARM Support Features and Benefits Advanced I/O High Capacity • 15 k to 1 M System Gates • Up to 144 kbits of True Dual-Port SRAM • Up to 300 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS


    Original
    PDF A3P250

    DUAL-PORT STATIC RAM

    Abstract: IC transistor linear handbook
    Text: ProASIC 3L Low-Power Handbook ProASIC3L Low-Power Flash Device Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – ProASICL Low-Power Datasheet


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    RT3PE3000

    Abstract: ycl pcb 452 kt 501 transistor 1N12 SP6-3 kt 803 a CEN 2N2222A 1437
    Text: Actel Fusion Mixed-Signal FPGA for the MicroBlade Advanced Mezzanine Card Solution Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i


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    bm 308 an

    Abstract: ICE 10501 TRANSISTOR MARKING YB 826
    Text: IGLOOe Handbook IGLOOe Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOOe Datasheet IGLOOe Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I


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