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    54LS114 Search Results

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    54LS114 Price and Stock

    Motorola Semiconductor Products 54LS114A/BCAJC

    IC,FLIP-FLOP,DUAL,J/K TYPE,LS-TTL,DIP,14PIN,CERAMIC
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    54LS114 Datasheets (14)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54LS114 National Semiconductor Original PDF
    54LS114 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    54LS114 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan PDF
    54LS114A/BCAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS114A/BDAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS114AM/B2AJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS114DM Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    54LS114DMQB National Semiconductor Original PDF
    54LS114DMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS114FM Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    54LS114FMQB National Semiconductor Original PDF
    54LS114FMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS114LMQB National Semiconductor Original PDF
    54LS114LMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF

    54LS114 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    LS114

    Abstract: 54LS114 54LS114DMQB 54LS114FMQB 54LS114LMQB C1995 E20A J14A W14B
    Text: 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’LS114 features individual J K and set inputs and common clock and common clear inputs When the clock goes HIGH the inputs are enabled and data will be accepted The


    Original     		54LS114 LS114 54LS114DMQB 54LS114FMQB 54LS114LMQB 54LS114 54LS114DMQB 54LS114LMQB C1995 E20A J14A W14B PDF

    ay-5-1012

    Abstract: ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor
    Text: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS


    Original     		38510/MACH Mll-M-38510 Z501300 Z501200 Z501201 Z012510 ZOl1510 ay-5-1012 ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor PDF

    Untitled

    Abstract: No abstract text available
    Text: M M O T O R O L A Military 54LS114A D u a l J -K Flip-Flop W ith Preset, C o m m o n C le ar and C o m m o n C lo c k MIL-M-38510/30105 T h e 5 4 L S 1 1 4 A o ffe rs c o m m o n clock a n d c o m m o n clear inputs and in d ivid u al J, K, and set inputs. Th e se m o n o lith ic dual flip -flo p s are


    OCR Scan     		MIL-M-38510/30105 PDF

    Untitled

    Abstract: No abstract text available
    Text: 8 < > M ilitary 54LS114A MOTOROLA Dual J -K Flip-Flop W ith P reset, Common C lear and Com m on C lock MPO MIL-M-38510/30105 unw The 54LS114A offers common clock and common clear inputs and individual J, K, and set Inputs. These monolithic dual flip-flops are


    OCR Scan     		54LS114A MIL-M-38510/30105 54LS114A JM38510/30105BXA 54LS114A/BXA= PDF

    LS114

    Abstract: No abstract text available
    Text: ^ National Semiconductor 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’L S 1 14 features individual J, K and set inputs and com­ mon clock and common clear inputs. When the clock goes HIGH the inputs are enabled and data will be accepted. The


    OCR Scan     		54LS114 LS114 LS114 PDF

    SN54LS114A

    Abstract: SN54S114 SN74 SN74LS114A SN74S114A LS114
    Text: 54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK MARCH 1973 —R EV ISED MARCH 1988 SN 54LS114A . SN 54S114 SN 74LS114A . SN 74S114A • Fully Buffered to Offer Maximum Isolation


    OCR Scan     		SN54LS114A, SN54S114, SN74LS114A, SN74S114A SN54S114. SN54LS114A SN54S114 SN74 SN74LS114A LS114 PDF

    Untitled

    Abstract: No abstract text available
    Text: M M O T O R O M ilitary 54LS114A L A Dual J -K Flip-Flop W ith P reset, Com m on C lear and Com m on C lock M MIL-M-38510/30105 P O H U M The 54LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are


    OCR Scan     		54LS114A MIL-M-38510/30105 54LS114A JM38510/30105BXA PDF

    Untitled

    Abstract: No abstract text available
    Text: 54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK M A R C H 1973 — R E V ISE D M A R C H 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance SN 54LS114A . SN 54S114


    OCR Scan     		SN54LS114A, SN54S114, SN74LS114A, SN74S114A 54LS114A 54S114 74LS114A 74S114A PDF

    Untitled

    Abstract: No abstract text available
    Text: 54LS114A. SN54S114, SN74LS114A, SN74S114A DUAL J K NEGATIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK _ MARCH 1973 —REVISED MARCH 1988 • Fully B u ffe re d to O ffe r M a x im u m Isolation


    OCR Scan     		SN54LS114A. SN54S114, SN74LS114A, SN74S114A 54S114 74LS114A 74S114A PDF

    74s188 programming

    Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
    Text: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE


    OCR Scan     		38510/MACH MIL-M-38510 74s188 programming 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions PDF

    74LS115

    Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
    Text: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25


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    SN74ALS123

    Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
    Text: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS


    OCR Scan     		MIL-M-38510 SN74ALS123 SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138 PDF

    dm8130

    Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
    Text: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408


    OCR Scan     		54H00 54L00 54LS00 54H01 54L01 54LS01 54L02 54LS02 54L03 54LS03 dm8130 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76 PDF

    DM74367

    Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
    Text: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,


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    LG color tv Circuit Diagram schematics

    Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
    Text: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS


    OCR Scan     		MIL-M-38510 38510/MACH 3186J Z501201 Z012510 Z011510 D022110 D022130 D021110 D021130 LG color tv Circuit Diagram schematics texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243 PDF

    SN7401

    Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
    Text: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package


    OCR Scan     		24-lead SN74S474 SN54S475 SN74S475 SN54S482 SN74S482 LCC4270 SN54490 SN74490 SN54LS490 SN7401 sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c PDF

    SN54LS114A

    Abstract: SN54S114 SN74 SN74LS114A SN74S114A
    Text: 54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK SDLS010 _ • Fully Buffered to Offer Maxim um Isolation from External Disturbance • Package Options Include Ceramic Carriers


    OCR Scan     		SDLS010 SN54LS114A, SN54S114, SN74LS114A, SN74S114A 1973-REVISED SN54LS114A SN54S114 SN74 SN74LS114A PDF

    2650B

    Abstract: wf vqc 10d alu 9308 d Signetics 2650 SN52723 2650 cpu 82S103 pipbug Signetics NE561 cd 75232
    Text: flcnCTICf ßii>ouiR/mos fflICROPROCEÍSOR DATfl mnnuni SIGNETICS reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible products. Signetics also assumes no responsibility for the


    OCR Scan     		PDF

    1n52408

    Abstract: 1N52428 zener SFC2311 78M12HM 21L02A 54175 IRS 9530 transistor 10116dc BB105G 962PC
    Text: Contents Fairchild Semiconductors Ltd. Solid State Scientific Inc. Diodes Ltd. Thomson C. S. F. B Ashcroft Electronics Ltd. Sprague Electric UK Ltd. Precision Dynamic Corp. B&R Relays Schrack Relays Heller mann Electric B Foreword We are pleased to present the latest edition of the BARLEC Catalogue, which


    OCR Scan     		301PT1115 302PT1115 303PT1115 311PT1110 312PTI110 319PTI110 327PTI110 351PT1115 353PT1115 1n52408 1N52428 zener SFC2311 78M12HM 21L02A 54175 IRS 9530 transistor 10116dc BB105G 962PC PDF

    FMK2

    Abstract: 74LS114 54LS114DM 54S114DM 54S114FM 74LS114DC 74LS114FC 74LS114PC 74S114DC 74S114FC
    Text: 114 CONNECTION DIAGRAM PIN O U T A 54S/74S114 54LS/74LS114 •Öl / f D \ t O 3 DUAL JK N E G A TIV E E D G E -T R IG G E R E D F L IP -F L O P Cd {T W ith C om m on C locks and Clears Ï 3 Vcc ETL K)[T Ki C P J i CD SD1 Qi Qi Ji |T n jc p Ü]K2 Soi[T DESCRIPTION— The '114 features individual J, K and set inputs and com­


    OCR Scan     		54S/74S114 54LS/74LS114 54/74S 54/74LS FMK2 74LS114 54LS114DM 54S114DM 54S114FM 74LS114DC 74LS114FC 74LS114PC 74S114DC 74S114FC PDF

    100414DC

    Abstract: 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501
    Text: FAIRMONT ELECTRONICS PTY. LTD. TE L.48-6421 4 8 -6 4 8 1 /2 /4 C AB LES ' FAIRTRONICS' C R A IG H A L L T E L E X 8-3227 S A . P O .BOX 41102, C R A IG H A LL 2024. I ouani v-ox 39! 262Bramley 2018 FAIRCHILD 464 Ellis Street, M ountain View, C alifornia 94042


    OCR Scan     		262Bramley orporation/464 962-5011/TWX 19-PIN 100414DC 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501 PDF

    74LS114

    Abstract: cpj2 8 pin dip j k flipflop ic
    Text: ' NATIONAL SENICOND -CLOCICJ OSE D | b SO llS S 00^37^1 7 | 114 ~ F m -0 7 -0 7 CO NNECTIO N DIAGRAM PINOUT A 54S/74S114 54LS/74LS114 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP c 5 [T ETL Ki T (With Common Clocks and Clears K i CP J t CO Sd ) Qi Ji [ T Oi


    OCR Scan     		54S/74S114 54LS/74LS114 54/74S 54/74LS 74LS114 cpj2 8 pin dip j k flipflop ic PDF

    74LS114A

    Abstract: No abstract text available
    Text: TYPES 54LS114A, SN54S114, SN74LS114A, SN74S114 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK REVISED DECEMBER 1983 Fully Buffered to O ffer M axim um Isolation fro m External Disturbance S N 54L S 114A , S N 5 4 S 1 1 4 . . . J OR W PACKAGE


    OCR Scan     		SN54LS114A, SN54S114, SN74LS114A, SN74S114 74LS114A PDF

    sn55470

    Abstract: 7544-1 transistor SN75326 SN7401 SN75426 54175 SN75270 SN55450 sn75493 National Semiconductor Linear Data Book
    Text: The Interface Circuits Data Book for Design Engineers First Edition IM P O R T A N T NO TICES Texas Instruments reserves the right to make changes at any tim e in order to im prove design and to supply the best product possible. T l cannot assume any responsibility for any circuits shown or


    OCR Scan     		PDF