m3230
Abstract: PQFP 176 Actel pdf on sram M3-2100 M32100 vq 44 quad flatpack 600 747 Actel part number M1020 M1225
Text: Actel Mask Programmed Gate Arrays Features • Available in commercial or industrial temperature ranges • Mask Programmed versions of Actel Field Programmable Gate Arrays FPGAs • PLCC, PQFP, VQFP, and TQFP packages available • Significant cost reduction for medium- to high-volume
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Z1601720ASC
Abstract: 100PIN VQFP 100-PIN Z16017 Z16M17 Z16M1720ASC Z86017 Z8601720ASC Z86M17 Z86M1720ASC
Text: Z86017 / Z16017 Reference Manual Zilog APPENDIX D. PACKAGING AND ORDERING INFORMATION 20 MHz PCMCIA Adapter Chips Z86017 Z86M17 Z16017 Z16M17 100-Pin VQFP Z8601720ASC 100-pin VQFP Z86M1720ASC 100-Pin VQFP Z1601720ASC 100-Pin VQFP Z16M1720ASC For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
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Z86017
Z16017
Z86017
Z86M17
Z16M17
100-Pin
Z8601720ASC
Z86M1720ASC
Z1601720ASC
100PIN VQFP
Z16017
Z16M17
Z16M1720ASC
Z8601720ASC
Z86M17
Z86M1720ASC
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PLC to pc Communication cables pin
Abstract: ELPAC Z87L02 Z87L0200ZEM EPP-100-QF49-W 100VQFP
Text: PRODUCT SPECIFICATION Z87L0200ZEM Z-PHONE EMULATOR FEATURES Supported Devices Packages Emulation OTP Programming 100-pin VQFP Z87L0216ASCR1 None 100-pin PQFP Z87L0216FSCR2 None 144-pin VQFP 3 None Z87L0316ASCR Notes: 1. Requires separately-purchased emulator pod EPP-100QF49-W.
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Z87L0200ZEM
100-pin
Z87L0216ASCR1
Z87L0216FSCR2
144-pin
Z87L0316ASCR
EPP-100QF49-W.
EPP-100QF63-W.
EPP-100QF06-W.
PLC to pc Communication cables pin
ELPAC
Z87L02
Z87L0200ZEM
EPP-100-QF49-W
100VQFP
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Untitled
Abstract: No abstract text available
Text: XC9572XV High-performance CPLD R DS052 v2.3 May 31, 2002 5 Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins)
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XC9572XV
DS052
XC9500XV
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Z86017
Abstract: ide 2.5 DASP Z16017 Z16M17 Z86M17 bus control request sequencer
Text: REFERENCE MANUAL 1 CHAPTER 1 Z86017/Z16017 PCMCIA INTERFACE OVERVIEW 1.1 FEATURES Device RAM Bytes Speed Package 256 256 256 256 20 20 20 20 100–Pin VQFP 100–Pin VQFP 100–Pin VQFP 100–Pin VQFP Z86017 Z86M17* Z16017 Z16M17* * Mirror Image Bond-Out Options
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Z86017/Z16017
Z86017
Z86M17*
Z16017
Z16M17*
Z86M17/Z16M17)
UM95HDD0101
Z86017
ide 2.5 DASP
Z16017
Z16M17
Z86M17
bus control request sequencer
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A3P250
Abstract: A3P060 A3P1000 Datasheet A3P125 IO97RSB2 IO52NDB1 FBGA A3P250 fbga 256 A3P250 ACTEL ACTEL FBGA 144
Text: Automotive ProASIC3 Packaging 3 – Package Pin Assignments 100-Pin VQFP 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at .
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100-Pin
A3P060
IO62RSB1
IO31RSB0
GAA2/IO51RSB1
A3P250
A3P1000
Datasheet A3P125
IO97RSB2
IO52NDB1
FBGA A3P250
fbga 256
A3P250 ACTEL
ACTEL FBGA 144
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Untitled
Abstract: No abstract text available
Text: XC9572XV High-performance CPLD R DS052 v2.4 June 18, 2003 5 Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins)
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XC9572XV
DS052
44-pin
48-pin
100-pin
72-user
54-input
220oC.
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PC44
Abstract: VQ44 XAPP361 XC9500XV XC9572XV
Text: XC9572XV High-performance CPLD R DS052 v2.5 August 21, 2003 5 Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins)
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XC9572XV
DS052
44-pin
48-pin
100-pin
72-user
54-input
220oC.
PC44
VQ44
XAPP361
XC9500XV
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DS052
Abstract: No abstract text available
Text: XC9572XV High-performance CPLD R DS052 v2.7 January 16, 2006 5 Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin VQFP (34 user I/O pins) - 100-pin TQFP (72-user I/O pins) Optimized for high-performance 2.5V systems
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XC9572XV
DS052
XC9500XV
220oC.
XCN05020.
DS052
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Z180 mpu
Abstract: S180 Z180 Z380 Z80181 Z80185 Z80189 Z80195 Zilog Z80 instruction set Z80182
Text: Datacom Block Diagram Z80/Z180 Embedded Controllers 16550 MIMIC ESCC 2 Ch SCC/2 (85C30/2) Z180 MPU 16 I/O 16550 MIMIC COM Port Enhanced Decode S180 MPU PC DMA Mailbox Z180 MPU 24 I/O CTC Device Zilog Superintegration Pr oducts Guide Z80181 IEEE 1284 32K
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Z80/Z180
85C30/2)
Z80181
Z80189
Z80182/Z8L182
Z80185
Z80195
Z80380/Z8L380
Z8L182
ZEPMIP00002
Z180 mpu
S180
Z180
Z380
Z80181
Z80185
Z80189
Z80195
Zilog Z80 instruction set
Z80182
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100-Pin CPGA Package Pin-Out Diagram
Abstract: 6.000 mhz QL12x16B-1PL68C 12x16B vqfp package pinout CF100 PF100 PL84 PV100 QL16X24B
Text: QL12x16B Wild Cat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA Rev B .2000 usable gates, 88 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.
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QL12x16B
12-by-16
68pin
84-pin
100-pin
100pin
16-bit
12x16B
100-Pin CPGA Package Pin-Out Diagram
6.000 mhz
QL12x16B-1PL68C
vqfp package pinout
CF100
PF100
PL84
PV100
QL16X24B
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actel vqfp
Abstract: IO87RSB1
Text: ProASIC3 nano Packaging 3 – Package Pin Assignments 48-Pin QFN Pin 1 48 1 Notes: 1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground GND . Note For Package Manufacturing and Environmental information, visit the Resource Center at
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48-Pin
A3PN010
GEC0/IO37RSB1
IO06RSB0
IO36RSB1
GDA0/IO05RSB0
GEA0/IO34RSB1
actel vqfp
IO87RSB1
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IO91RSB2
Abstract: Datasheet AGLN060 81-Pin Datasheet AGLN020 AGLN020 IO10RSB0 AGLN010
Text: IGLOO nano Packaging 3 – Package Pin Assignments 36-Pin UC Pin 1 Pad Corner 6 5 4 3 2 1 A B C D E F Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at .
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36-Pin
AGLN010
IO21RSB1
IO18RSB1
IO13RSB1
GDC0/IO00RSB0
IO06RSB0
GDA0/IO04RSB0
GEC0/IO37RSB1
IO91RSB2
Datasheet AGLN060
81-Pin
Datasheet AGLN020
AGLN020
IO10RSB0
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Untitled
Abstract: No abstract text available
Text: XC9572XL High Performance CPLD R DS057 v1.5 July 15, 2004 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell
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XC9572XL
DS057
XC9500XL
220oC.
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xc9572xl pin configuration
Abstract: XC9572XL TQG100 XC9572XL-10VQG44I xc9572xl XC9572XL-10TQG100C XC9572XL-10-TQ100 xc9572xl pin XC9572XL-10TQG100I VQ64 XC9572XL-7VQG64I
Text: XC9572XL High Performance CPLD R DS057 v1.7 April 29, 2005 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell
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XC9572XL
DS057
44-pin
48-pin
64-pin
100-pin
220oC.
xc9572xl pin configuration
XC9572XL TQG100
XC9572XL-10VQG44I
XC9572XL-10TQG100C
XC9572XL-10-TQ100
xc9572xl pin
XC9572XL-10TQG100I
VQ64
XC9572XL-7VQG64I
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XC9572XL
Abstract: xc9572xl pin configuration XC9572XL-5VQ44C XAPP114 XAPP427 XC9500XL XC9572 XC9572XL-10 XC9572XL-5 XC9572XL-7
Text: XC9572XL High Performance CPLD R DS057 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell
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XC9572XL
DS057
XC9500XL
220oC.
xc9572xl pin configuration
XC9572XL-5VQ44C
XAPP114
XAPP427
XC9572
XC9572XL-10
XC9572XL-5
XC9572XL-7
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xc9572xl pin configuration
Abstract: XC9572XL XC9572XL-10PCG44C XC9572XL-10CS48I XC9572XL-10VQG44C XC9572XL-7TQ100C XC9572XL-10PC44C xc9572xl-10PCG44C pin XC9572XL-7PCG44C XC9572XL-5TQG100C
Text: XC9572XL High Performance CPLD R DS057 v2.0 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)
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XC9572XL
DS057
44-pin
48-pin
64-pin
100-pin
220oC.
xc9572xl pin configuration
XC9572XL-10PCG44C
XC9572XL-10CS48I
XC9572XL-10VQG44C
XC9572XL-7TQ100C
XC9572XL-10PC44C
xc9572xl-10PCG44C pin
XC9572XL-7PCG44C
XC9572XL-5TQG100C
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xc9572xl
Abstract: XC9572XL-10VQG44I XC9572XL TQG100 xc9572xl pin xc9572xl pin configuration XC9572XL-5PCG44C TQFP 144 PACKAGE footprint DS058 XC9572XL-5VQG44C XC9572XL-7PC44
Text: XC9572XL High Performance CPLD R DS057 v1.9 March 22, 2006 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell
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XC9572XL
DS057
44-pin
48-pin
64-pin
100-pin
220oC.
XC9572XL-10VQG44I
XC9572XL TQG100
xc9572xl pin
xc9572xl pin configuration
XC9572XL-5PCG44C
TQFP 144 PACKAGE footprint
DS058
XC9572XL-5VQG44C
XC9572XL-7PC44
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Untitled
Abstract: No abstract text available
Text: QL12X16B Wildcat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA R ev B P High Usable Density - A 12 -by-16 array o f 192 logic cells provides 6,000 total available gates, w ith 2000 typically usable "gate array" gates in 68pin and 84-pin PLCC, 84-pin CPGA , 100-pin CQFP, 100-pin VQFP, and 100pin TQ FP packages.
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QL12X16B
-by-16
68pin
84-pin
100-pin
100pin
16-bit
M/883C
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TTL Logic Family list
Abstract: PQFP 176
Text: Actel Mask Programmed Gate Arrays F e a tu re s • Available in comm ercial or industrial tem perature ranges • • PLCC, PQFP, VQFP, and TQFP packages available • • Significant cost reduction for medium- to high-volume applications Meets all internal worst-case FPGA perform ance
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1200X15
TTL Logic Family list
PQFP 176
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PQFP 176
Abstract: No abstract text available
Text: Actel Mask Programmed Gate Arrays F eatu res • Available in commercial or industrial temperature ranges • • PLCC, PQFP, VQFP, and TQFP packages available • Meets all internal worst-case FPGA performance specifications • Lower I/O capacitance than FPGA
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GGD2727
PQFP 176
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Zilog Z80 KIO
Abstract: Z84C9008ASC TCC-100 Z84C9008 Z84C9008VSC Z80 KIO Z84C9008VEC
Text: C u s t o m e r P r o c u r e m e n t S p e c if ic a t io n Z84C90 KIO S erial /P arallel / C ounter /T imer FEATURES Table 1. Z84C9008 KIO Serial/ Parallel/Counter/Timer Part Number Package Z84C9008ASC Z84C9008XXX1380 Z84C9008VEC Z84C9008VSC 100-pin VQFP
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Z84C90
Z84C9008
Z84C9008ASC
Z84C9008XXX1380
Z84C9008VEC
Z84C9008VSC
100-pin
84-pin
Zilog Z80 KIO
TCC-100
Z80 KIO
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Untitled
Abstract: No abstract text available
Text: QL12x16B WildCat 2000 Yery-High-Speed 2K 6K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS .2000 usable gates, 88 I/O pins Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.
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QL12x16B
12-by-16
68pin
84-pin
100-pinCQFP,
100-pin
100pin
16-bit
12xl6B
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Untitled
Abstract: No abstract text available
Text: Actel Mask Programmed Gate Arrays F e a tu re s D e s c rip tio n Mask Programmed versions of Actel Field Programmable Gate Arrays FPGAs Significant cost reduction for medium- to high-volume applications Pin-for-pin compatible with Actel FPGAs PCI Local Bus Revision 2 Compliant
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M1440
176-Pin
011241b
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