CY7C1022
Abstract: No abstract text available
Text: Y7C10 PRELIMINARY Y7C1022 32K x 16 Static RAM Features • 5.0V operation ± 10% • High speed — tAA = 12 ns • Low active power — 825 mW (max., 10 ns, “L” version) • Very Low standby power — 500 µW (max., “L” version) • Automatic power-down when deselected
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Y7C10
CY7C1022
400-mil
CY7C1022
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CY7C1020
Abstract: No abstract text available
Text: Y7C10 PRELIMINARY Y7C1020 32K x 16 Static RAM Features BLE is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0 through A 14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14).
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Y7C10
CY7C1020
I/O16)
44-pin
400-mil
44-Lead
400-Mil)
CY7C1020-15ZC
44-Lead
CY7C1020L-15ZC
CY7C1020
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CY7C1022
Abstract: No abstract text available
Text: fax id: 1105 Y7C10 PRELIMINARY Y7C1022 32K x 16 Static RAM Features • 5.0V operation ± 10% • High speed — tAA = 12 ns • Low active power — 825 mW (max., 10 ns, “L” version) • Very Low standby power — 500 µW (max., “L” version) • Automatic power-down when deselected
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Y7C10
CY7C1022
400-mil
CY7C1022
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CY7C1020
Abstract: No abstract text available
Text: fax id: 1074 Y7C10 PRELIMINARY Y7C1020 32K x 16 Static RAM Features BLE is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14).
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Y7C10
CY7C1020
I/O16)
44-pin
400-mil
CY7C1020
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80486 microprocessor block diagram and pin diagram
Abstract: WCSS0418V1F WCSS0418V1F-117
Text: Y7C1032 WCSS0418V1F 256K x 18 Synchronous 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 256K by 18 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wrap-around counter supporting either interleaved or linear burst sequence
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Y7C1032
WCSS0418V1F
117-MHz
100-pin
WCSS0418V1F
selectedBG119
BG119
119-Ball
100-Lead
80486 microprocessor block diagram and pin diagram
WCSS0418V1F-117
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Untitled
Abstract: No abstract text available
Text: fax id: 1089 =mmmm rrm - Y7C1009V33 C Y7C109 V33 PRELIMINARY 128K x 8 Static RAM memory expansion is provided by an active LOW chip enable CE-| , an active HIGH chip enable (CE2), an active LOW out put enable (OE), and three-state drivers. Writing to the device
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CY7C1009V33
Y7C109
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adsh 13
Abstract: intel 80486 CY7C1031 CY7C1032 VXXXX
Text: Y7C1031 Y7C1032 PRELIMINARY ?CYPRESS Functional Description continued Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) is LOW and (2) AD5P is LOW. ADSP-triggered write cycles are completed in two clock periods. The address at Ao
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CY7C1031
CY7C1032
CY7C1031
CY7C1032will
52-Lead
CY7C1032-
CY7C1032â
CY7C1032-8NC
adsh 13
intel 80486
CY7C1032
VXXXX
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Untitled
Abstract: No abstract text available
Text: 7C101A: 11-25-91 Revision: Thursday, February 18,1993 Y7C101A Y7C102A k ' Vwt S3 « 3 PRELIMINARY 7J= CYPRESS SEMICONDUCTOR 256K x 4 Static RAM with Separate I/O Features Functional Description • Highspeed — tAA = 12 ns • Transparent write 7C101A
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7C101A:
CY7C101A
CY7C102A
7C101A)
CY7C101Aand
CY7C102Aare
in982.
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Untitled
Abstract: No abstract text available
Text: fax id: 1047 Y7C109 Y7C1009 ^C YPR ESS 128K x 8 Static RAM active HIGH chip enable CE 2 , an active LOW output enable (OE), and three-state drivers. Writing to the device is accom plished by taking chip enable one (CE-|) and write enable (WE) inputs LOW and chip enable two (CE 2 ) input HIGH. Data on
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CY7C109
CY7C1009
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Untitled
Abstract: No abstract text available
Text: fax id: 1052 W Y7C106 Y7C1006 / C Y P R E S S _ 256K x 4 Static RAM an active LO W o u tp u t enable OE , and th re e -sta te drivers. T h e se devices have an au tom atic pow e r-d ow n fea tu re th a t re du ces pow er con sum p tion by m ore than 65% w h e n th e d e vic
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CY7C106
CY7C1006
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Untitled
Abstract: No abstract text available
Text: fax id: 1047 C Y 7 C 1 0 9 C Y 7 C 1 0 0 9 w / C Y P R E S S 128K x 8 Static RAM Features active HIG H chip enable C E 2 , an active LO W o u tp u t enable (OE), and th re e -sta te drivers. W riting to the device is acco m plished by takin g chip enable one (CE-|) and w rite enable (WE)
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CY7C1049
Abstract: CY7C1049L
Text: fax id: 1082 S b M IM Ì F T V fS T“ ¡T* &*• r i s I a ÆÊ l i i J F ; U F lm Y7C1049 Y7C1049L PRELIMINARY ß b ö 512 K x 8 Static RAM Features is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de
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CY7C1049
CY7C1049L
512Kx
CY7C1049L
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Untitled
Abstract: No abstract text available
Text: fax id: 1075 Y7C1020V _ 3 2 K x 16 Static RAM BLE is LOW, then data from I/O pins (l/O-j through l/0 8), is written into the location specified on the address pins (A0 through A 14). If byte high enable (BHE) is LOW, then data from I/O pins (l/0 9 through l/O i6) is written into the location speci
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CY7C1020V
44-pin
400-mil
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY f CYPRESS 256K x 4 Static RAM with Separate I/O Features Functional Description • High speed t h e Y7C1001 and Y7C1002 are highperform ajice C M O S static RA M s orga nized as 262,144 x 4 bits with separate I/O. Easy m em ory expansion is provided by ac
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CY7C1001
CY7C1002
7C1001)
7C1001
25int
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en 10204 3.2
Abstract: No abstract text available
Text: fax id: 1074 Y7C1020 C'i- P R E L I M I N A R Y 32Kx 16 Static RAM BLE is LOW, then data from I/O pins (l/0-| through l/0 8), is written into the location specified on the address pins (A0 through A 14). If byte high enable (BHE) is LOW, then data from
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CY7C1020
44-pin
400-mil
en 10204 3.2
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CY7C1021
Abstract: CY7C1021-20ZC TA7291 A12C A15C LUM512
Text: ^— — —j PVDD17Q Q %a m m * r u l i n n o PRELIMINARY Y7C1021 o 64K Features X 16 Static RAM BLE is LOW, then data from I/O pins (I/O-) through l/0 8), is written into the location specified on the address pins (A0 through A-|5). If byte high enable (BHE) is LOW, then data from
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CY7C1021
44-pin
400-mil
CY7C1021-20ZC
TA7291
A12C
A15C
LUM512
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1A8CN
Abstract: No abstract text available
Text: fax id: 1074 Y7C1020 3 2 K x 16 Static RAM BLE is LOW, then data from I/O pins (l/0-| through l/0 8), is written into the location specified on the address pins (A0 through A 14). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through l/0-|6) is written into the location speci
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CY7C1020
1A8CN
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AG262
Abstract: 1009V33-20VC 7C109V33
Text: fax id: 1089 C'i- Y7C1009V33 Y7C109V33 PRELIMINARY 1 2 8 K x 8 S ta tic Features R A M memory expansion is provided by an active LOW chip enable CE-| , an active HIGH chip enable (CE2), an active LOW out put enable (UF), and three-state drivers. Writing to the device
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CY7C1009V33
CY7C109V33
AG262
1009V33-20VC
7C109V33
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CY7C1021
Abstract: TA7291
Text: ; PRELIMINARY Y7C1021 O i l h iib b 64K Features X 16 Static RAM BLE is LOW, then data from I/O pins (I/O-) through l/0 8), is written into the location specified on the address pins (A0 through A-|5). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through l/0 -|6) is written into the location speci
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CY7C1021
44-pin
400-mil
CY7C1021
TA7291
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CY7C107A
Abstract: A7AE
Text: 1M x 1 Static RAM Features Functional D escription • High speed — tAA = 12 ns • CMOS for optimum speed/power • Low active power T he Y7C107A is a high-perform ance CM OS static R A M organized as 1,048,576 words by 1 bit. Easy m em ory expansion is
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CY7C107A
CY7C107A
400-Mil)
CY7C107A-35DMB
28-Lead
8-00232-A
0D1472B
A7AE
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Untitled
Abstract: No abstract text available
Text: Y7C1031 Y7C1032 PRELIMINARY ?CYPRESS Functional Description continued Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) is LOW and (2) AD5P is LOW. ADSP-triggered write cycles are completed in two clock periods. The address at Ao
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CY7C1031
CY7C1032
CY7C1031
CY7C1032
CY7C1032â
52-Lead
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Untitled
Abstract: No abstract text available
Text: 7c1007: 1 1 -2 5 -9 1 Revision: Monday, December 2 1 ,1992 ^?1A R S3 1983 Y7C1007 PRELIMINARY CYPRESS '. SEMICONDUCTOR 1M x 1 Static RAM Features Functional Description • H ighspeed — tAA — 12 ns • CMOS for optimum speed/power • Low active power
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7c1007:
CY7C1007
CY7C1007
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