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    XC9536 Price and Stock

    AMD XC9536XL-10VQG44I

    IC CPLD 36MC 10NS 44VQFP
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    DigiKey XC9536XL-10VQG44I Tray 80,974 1
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    AMD XC9536XL-7VQG44I

    IC CPLD 36MC 7.5NS 44VQFP
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    DigiKey XC9536XL-7VQG44I Tray 6,474 1
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    AMD XC9536XL-10VQG64I

    IC CPLD 36MC 10NS 64VQFP
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    DigiKey XC9536XL-10VQG64I Tray 50 1
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    AMD XC9536-15PC44C

    IC CPLD 36MC 15NS 44PLCC
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    AMD XC9536-15VQ44C

    IC CPLD 36MC 15NS 44VQFP
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    XC9536 Datasheets (249)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    XC9536 Xilinx The Programmable Logic Data Book Original PDF
    XC9536 Xilinx In-System Programmable CPLD Family Original PDF
    XC9536 Xilinx XC9536 In-System Programmable CPLD Original PDF
    XC9536-10 Xilinx XC9536 In-System Programmable CPLD Original PDF
    XC9536-10CS48C Xilinx In-System Programmable CPLD Original PDF
    XC9536-10CS48C Xilinx In-system programmable CPLD. Speed 10ns pin-to-pin delay. Original PDF
    XC9536-10CS48C Xilinx In-System Programmable CPLD Original PDF
    XC9536-10CS48C Xilinx XC9536-10CS48C - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC9536-10CS48I Xilinx XC9536 In-System Programmable CPLD Original PDF
    XC9536-10CS48I Xilinx XC9536-10CS48I - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC9536-10CSG48C Xilinx XC9536-10CSG48C - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC9536-10CSG48I Xilinx XC9536-10CSG48I - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC9536-10PC44C Xilinx In-system programmable CPLD. Speed 10ns pin-to-pin delay. Original PDF
    XC9536-10PC44C Xilinx In-System Programmable CPLD Original PDF
    XC9536-10PC44C Xilinx XC9536-10PC44C - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC9536-10PC44C Xilinx In-System Programmable CPLD Original PDF
    XC9536-10PC44C Xilinx Over 600 obsolete distributor catalogs now available on the Datasheet Archive - CMOS CPLD, 36 Macrocells, 2 Func Blks, 36 Regs, 10ns, Pkg Style 44 Lead PLCC Scan PDF
    XC9536-10PC44I Xilinx In-System Programmable CPLD Original PDF
    XC9536-10PC44I Xilinx In-System Programmable CPLD Original PDF
    XC9536-10PC44I Xilinx XC9536-10PC44I - NOT RECOMMENDED for NEW DESIGN Original PDF
    ...

    XC9536 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    XC9536XL

    Abstract: XAPP114 XAPP427 XC9500XL XC9536 Pb-Free Marking Codes XC9536XL VQFP XC9536XL-10VQ64C VQG44 XC9536XL-10VQ44
    Text: XC9536XL High Performance CPLD R DS058 v1.7 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC9536XL DS058 XC9500XL 220oC. XAPP114 XAPP427 XC9536 Pb-Free Marking Codes XC9536XL VQFP XC9536XL-10VQ64C VQG44 XC9536XL-10VQ44

    XC9536

    Abstract: XC9536-6 XC9536-7 XC9500 XC9536-10 XC9536-15 XC9536-5 xc9536 44 pin vqfp
    Text: 9 1 XC9536 In-System Programmable CPLD  December 4, 1998 Version 5.0 1 1* Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins


    Original     		PDF XC9536 36V18 XC9536 XC9536-6 XC9536-7 XC9500 XC9536-10 XC9536-15 XC9536-5 xc9536 44 pin vqfp

    Untitled

    Abstract: No abstract text available
    Text: XC9536XV High-performance CPLD R DS053 v2.4 May 27, 2003 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)


    Original     		PDF XC9536XV DS053 44-pin 48-pin 54-input 220oC.

    PC44

    Abstract: XAPP361 XC9500XV XC9536XL XC9536XV B1.66 20E2
    Text: XC9536XV High-performance CPLD R DS053 v2.5 August 21, 2003 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)


    Original     		PDF XC9536XV DS053 44-pin 48-pin 54-input 220oC. PC44 XAPP361 XC9500XV XC9536XL B1.66 20E2

    leaflet

    Abstract: No abstract text available
    Text: WLP Wafer ( Level Package g ) New Product Leaflet XC6602,XC9235/36/37 Series デジカメ スマートフォン ノートPC WLPとはWafer Level Packageの略でチップサイズの超小型パッケー ジです。 XC6602シリーズ(LDOレギュレータ)、XC9235/XC9536/XC9237シリー


    Original     		PDF XC6602 XC9235/36/37 XC6602ã XC9235/XC9536/XC9237ã XC9235/XC9236/XC9237ã XC6602 100mA) OT-26W WLP-5-02 leaflet

    XC9536-10PC44C

    Abstract: No abstract text available
    Text: XC9536 In-System Programmable CPLD R DS064 v6.0 June 18, 2003 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable


    Original     		PDF XC9536 DS064 36V18 XC9536-10PC44C

    xilinx MARKING CODE

    Abstract: No abstract text available
    Text: XC9536XV High-performance CPLD R DS053 v2.7 January 16, 2006 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint package - 44-pin VQFP (34 user I/O pins) Optimized for high-performance 2.5V systems


    Original     		PDF XC9536XV DS053 XC9500XV 220oC. XCN05020. xilinx MARKING CODE

    Untitled

    Abstract: No abstract text available
    Text: Product Obsolete/Under Obsolescence XC9536XV High-performance CPLD R DS053 v3.0 June 25, 2007 1 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices


    Original     		PDF XC9536XV DS053 XC9536XL XCN07010 220oC. XCN05020.

    XC9536

    Abstract: xc9536 44 pin PC44 XC9536-10 XC9536-15 XC9536-5 XC9536-7 36V18 X5952
    Text:  XC9536 In-System Programmable CPLD June 1, 1996 Version 1.0 Preliminary Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power


    Original     		PDF XC9536 36V18 44-Pin X5952 PQ100 XC9536 TQ100 xc9536 44 pin PC44 XC9536-10 XC9536-15 XC9536-5 XC9536-7 X5952

    xilinx xc9536 Schematic

    Abstract: Xilinx jtag cable pcb Schematic Abel code for johnson counter xilinx vhdl code for 555 timer XC9536 vhdl code for 555 XAPP XC9536 PIN CONNECTION code voltage regulator vhdl LM2940CT-5
    Text:  XAPP 078 March, 1997 Version 1.0 XC9536 ISP Demo Board Application Note Summary The demo board described in this application note is a tool for demonstrating the In-System Programming (ISP) capabilities of the XC9500 CPLD family. Xilinx Family XC9500


    Original     		PDF XC9536 XC9500 XC9500 xilinx xc9536 Schematic Xilinx jtag cable pcb Schematic Abel code for johnson counter xilinx vhdl code for 555 timer vhdl code for 555 XAPP XC9536 PIN CONNECTION code voltage regulator vhdl LM2940CT-5

    XC95XX

    Abstract: XAPP361 XC9500XV XC9536XL XC9536XV XCN07010 xilinx MARKING CODE XCN05020 mclp
    Text: XC9536XV High-performance CPLD R DS053 v3.0 June 25, 2007 1 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to


    Original     		PDF XC9536XV DS053 XC9536XL XCN07010 44-pin 220oC. XCN05020. XC95XX XAPP361 XC9500XV xilinx MARKING CODE XCN05020 mclp

    7CS4

    Abstract: PC44 XAPP361 XC9500XV XC9536XL XC9536XV c71021 XC9536XL vq44 54V18
    Text: XC9536XV High-performance CPLD R DS053 v2.3 May 31, 2002 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)


    Original     		PDF XC9536XV DS053 44-pin 48-pin 54-input 7CS4 PC44 XAPP361 XC9500XV XC9536XL c71021 XC9536XL vq44 54V18

    XC9500

    Abstract: XC9536 XC9536-10 XC9536-15 XC9536-5 XC9536-6 XC9536-7
    Text: 9 XC9536 In-System Programmable CPLD  June 3, 1998 Version 3.0 3* Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power


    Original     		PDF XC9536 44-Pin 48-Pin XC9536 XC9500 XC9536-10 XC9536-15 XC9536-5 XC9536-6 XC9536-7

    9536

    Abstract: XC9500 XC9536 XC9536-10 XC9536-15 XC9536-5 XC9536-6 XC9536-7
    Text: 9 1 XC9536 In-System Programmable CPLD  December 4, 1998 Version 5.0 1 1* Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins


    Original     		PDF XC9536 36V18 XC9536 9536 XC9500 XC9536-10 XC9536-15 XC9536-5 XC9536-6 XC9536-7

    54V18

    Abstract: No abstract text available
    Text: XC9536XV High-performance CPLD R DS053 v2.0 January 29, 2001 1 Advance Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC9536XV DS053 44-pin 48-pin 54-input 54V18

    xc9536

    Abstract: xc9536-7vq44 95xxx XC9536-7VQ44I xc9536-15vq44i XC9536-15VQ44C
    Text: XC9536 In-System Programmable CPLD R DS064 v6.2 April 15, 2005 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable


    Original     		PDF XC9536 DS064 36V18 xc9536-7vq44 95xxx XC9536-7VQ44I xc9536-15vq44i XC9536-15VQ44C

    54V18

    Abstract: No abstract text available
    Text: XC9536XL High Performance CPLD R DS058 v1.3 October 21, 2002 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC9536XL DS058 44-pin 48-pin 64-pin 54V18

    xc9536

    Abstract: XCN11010 xc9536 44 pin XILINX XC9536 xc9536 vqg44 xc9536-7vq44 XC9536-7VQG44I XC9536-7PCG44I XC9536-10VQ44C XC9536-15PCG44I
    Text: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – XC9536 In-System Programmable CPLD R DS064 v7.0 May 17, 2013 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates


    Original     		PDF XC9536 DS064 36V18 XCN11010 xc9536 44 pin XILINX XC9536 xc9536 vqg44 xc9536-7vq44 XC9536-7VQG44I XC9536-7PCG44I XC9536-10VQ44C XC9536-15PCG44I

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X XC9536 In-System Programmable CPLD October 29, 1997 Version 2.0 Product Specification Features Power Management 5 ns pin-to-pin logic delays on all pins • • • • • • • • • • • • • fcNT to MHz 36 macrocells with 800 usable gates


    OCR Scan     		PDF XC9536 36V18 44-Pin XC9536

    Untitled

    Abstract: No abstract text available
    Text: XC9536 In-System Programmable CPLD K X I L I N X June 1, 1996 Version 1.0 Preliminary Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fQisiy to 125 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins


    OCR Scan     		PDF XC9536 36V18 DDD72b2 44-Pin TT4175T

    xc9536 44 pin vqfp

    Abstract: No abstract text available
    Text: £ XILINX XC9536 In-System Programmable CPLD June 3 ,1 9 9 8 Version 3.0 Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC9536 by config­ uring macrocells to standard or low-power modes of opera­


    OCR Scan     		PDF XC9536 36V18 16-bit X5919 xc9536 44 pin vqfp

    Untitled

    Abstract: No abstract text available
    Text: flXIUNX XC9536 In-System Programmable CPLD November 2,1998 Version 4.0 Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC9536 by config­ uring macrocells to standard or low-power modes of opera­


    OCR Scan     		PDF XC9536 36V18 44-Pin 48-Pin XC9536

    Untitled

    Abstract: No abstract text available
    Text: HXILINX XC9536 In-System Programmable CPLD Novem ber 2, 1998 Version 4.0 Product Specification Features Power Management • 5 ns pin-to-pin logic delays on all pins • ^CNT to 100 MHz • • • 36 m acrocells with 800 usable gates Up to 34 user I/O pins


    OCR Scan     		PDF XC9536 36V18 S-026-AC S-086-AC -026-A

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X XC9536 In-System Programmable CPLD November 10, 1997 Version 2.0 Product Specification Features Power Management • 5 ns pin-to-pin logic delays on all pins • • • • fcNT to MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins


    OCR Scan     		PDF XC9536 36V18 44-Pin XC9536