XRS10L240
Abstract: 22 pin sata female Connector SMD HEADER 5X2 10n capacitor C8051F32 SMD FET j11
Text: SOTP1 SOTN1 SOTP2 SOTN2 8 7 SOTP2 SOTN2 SOTP3 SOTN3 19 20 SOTP3 SOTN3 SORP0 SORN0 65 66 SORP0 SORN0 SORP1 SORN1 60 59 SORP1 SORN1 SORP2 SORN2 11 10 SORP2 SORN2 SORP3 SORN3 16 17 SORP3 SORN3 SITP0 SITN0 93 94 SITP0 SITN0 SITP1 SITN1 82 81 SITP1 SITN1 SIRP0
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MAX8869
XRS10L240)
XRS10L240
22 pin sata female Connector
SMD HEADER 5X2
10n capacitor
C8051F32
SMD FET j11
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ni usb 6212
Abstract: SS-00259-1 C2060 C2055 C2068 quanta C2096 R2067 915GM SW1010CPT
Text: 1 2 3 4 5 478 PIN micro FC-PGA 14, 15, 15w , 17w inch XGA, SXGA+ A LVDS LCD P7 P3,4 400/533 MHz A LVDS Alviso DVI M24/M26 UNBUFFERED DDRII SODIMM DDRII 400/533 P10 915GM/PM R/G/B CRT P9 R/G/B UNBUFFERED DDRII SODIMM DDRII 400/533 1257 PIN (micro FCBGA) PCIE 16Lanes
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M24/M26
915GM/PM
16Lanes
88E8053
ALC260
31x31mm)
TI-TPA6011A4
33MHZ
VT6212
11a/b/g
ni usb 6212
SS-00259-1
C2060
C2055
C2068
quanta
C2096
R2067
915GM
SW1010CPT
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Calistoga
Abstract: ALC861 VSS011 DMI0TXP OZ128TN ALC880 SAMA5
Text: Chapter2 Page 1 of 45 Major Components Chapter2 Major Components 2.1. System Block Diagram ……………………………………………… 3 2.2. Major Component Definition .…….………………………………. 35 2.3. Connector Definition…….………………………………………….
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FSB533/667
M52-T
SO-DIMM1/533/667
SO-DIMM2/533/667
945PM
16X16
16X16
QT4532KL080HC
Z3418
Z3419
Calistoga
ALC861
VSS011
DMI0TXP
OZ128TN
ALC880
SAMA5
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ICS9LP306
Abstract: Inventec SC7652 KBC1021 Inventec VAIL 2.0 kahuna rqa130n03 1981HD 51117 TP772
Text: GALLO 1.0 PV BUILD 2006.02.08 EE DATE POWER DATE DRAWER DESIGN CHECK RESPONSIBLE DATE CHANGE NO. REV 3 SIZE = FILE NAME : XXXX-XXXXXX-XX XXXXXXXXXXXX P/N INVENTEC TITLE VER : GALLO 1.0 SIZE CODE A3 CS SHEET REV DOC. NUMBER Model_No 1 OF A01 58 TABLE OF CONTENTS
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R5000
D5000
R5004
SW5004
21SUYC
S5005
S5004
S5001
C5002
1000PF
ICS9LP306
Inventec
SC7652
KBC1021
Inventec VAIL 2.0
kahuna
rqa130n03
1981HD
51117
TP772
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C6198
Abstract: a17 c178 100v 12p quanta TMS 3617 CX20468-31 mtp42 cpu c644 100v 27p capacitor 100u 63V a70 4013 100 12p Quanta KT2
Text: 5 4 3 2 PCB Rev: A 1 Sch ver : 20040402_07 KT2 BLOCK DIAGRAM D PCB STACK UP LAYER 1 : TOP D PENTIUM-M / Montara-GM / ICH4-M LAYER 2 : GND LAYER 3 : IN1 CPU PENTIUM-M CPU THERMAL SENSOR LAYER 4 : IN2 GMT-781 478 Pins micro FC-PGA PAGE: 3 LAYER 5 : VCC 14.318MHz
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4X100MHZ
GMT-781
318MHz
CY28346/
ICS950810
MAX1907
MAX1999
266MHz
DTC144EUA
2N7002E
C6198
a17 c178 100v 12p
quanta
TMS 3617
CX20468-31
mtp42
cpu c644 100v 27p
capacitor 100u 63V
a70 4013 100 12p
Quanta KT2
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tps51620
Abstract: fds8884 tps51125 Inventec MPLC0730 AM4825P r5c804 TP889 hp d530 crb tps51125 kbc
Text: www.laptop-schematics.com INVENTEC Preliminary Test 2008/03/25 EE DATE POWER DATE DRAWER DESIGN CHECK RESPONSIBLE DATE CHANGE NO. REV 3 SIZE = FILE NAME : XXXX-XXXXXX-XX P/N XXXXXXXXXXXX INVENTEC TITLE VER : Preliminary Test SIZE CODE A3 CS DOC. NUMBER REV
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IEC951098
1-Nov-2007
tps51620
fds8884
tps51125
Inventec
MPLC0730
AM4825P
r5c804
TP889
hp d530 crb
tps51125 kbc
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quanta
Abstract: foxconn DD0ZL1LC301 ICH4 MTW355 USBP220 RN901
Text: 1 2 3 4 5 6 7 8 5VPCU 5V / 3.3V / 12V 3V_ALWAYS Page : 10 +12V Centrino CLOCK GEN CYPRESS CY28346-2 Page : 10 +5V 3V_S5 INTEL Mobile_479 CPU CLOCK S/S ICS *IC91718 A 5V_S5 3VSUS Page : 10 HOST BUS 400MHz CLK_SDRAM0~5, CLK_SDRAM0~5# 2.5VSUS Page : 10 Page : 2 , 3
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CY28346-2
M11-P
IC91718
400MHz
333MHZ
82855GME
31ZL1MB0004
quanta
foxconn
DD0ZL1LC301
ICH4
MTW355
USBP220
RN901
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TTL74194
Abstract: TC40H194P
Text: TOSHIBA INTEGRATED CIRCUIT TECHNICAL DATA P / F 1 r / I T P d n U I Q A I U T U il l i n TC40H194 C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4-B IT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER The TC40H194 is a 4-bit bidirectional bit register, which permits right shift in the direc
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TC40H194
TC40H194
TTL74194
LSTTL74LS194.
Ta-25
-15pF)
TC40H194P/F
TC40H194P
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01OJ
Abstract: No abstract text available
Text: TC4027BIVBF C zM O S DIGITAL IN T E G RA T E D CIRCUIT S ILIC O N M O N OLITH IC TC4027BP/TC4027BF DUAL J-K MASTER-SLAVE FLIP-FLOP TC4027BP/BF is J-K master-slave flip-flop having RESET and SET functions. In the case of J-K made, when the clock input is given with both RESET and SET at "L", the output
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TC4027BIVBF
TC4027BP/TC4027BF
TC4027BP/BF
TC4027BP/BF
01OJ
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LC4020B
Abstract: No abstract text available
Text: SANYO SEMI CON DUCTOR Tee d I CORP dqosvtq IIG 4 0 2 0 B : . *.-••* • .• •>» . ■ ■ ■ • - .-C,1 "" '■V- \• 3006b ••. .i •-i! V . . ;■ ' CM O S Standard Logic LC4000B Series 14-Stage Binary Counter 14 9 4B The LC4020B is an asynchronous reset function-provided l4-3tage ripple-carry
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3006b
LC4000B
14-Stage
LC4020B
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TC4008BP
Abstract: tc4008 t05V
Text: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4008BP TC4008BP 4-BIT FULL ADDER_ TC4008BP is full adder of 4 bit parallel processing type equipped with high speed parallel carry circuit. The sum of binary inputs applied to four augend data
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TC4008BP
TC4008BP
tc4008
t05V
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TC40H161P
Abstract: TC40H160P TC40H161 tc40h182 TC40H161P/F-
Text: TOSHIBA INTEGRATED CIRCUIT TECHNICAL DATA T C 4 0 H 1 6 0 P/F •T C 4 0 H 1 6 2 P/F . SILICON MONOLITHIC T C 4 0 H 1 61 P / F * T C 4 0 H 1 6 3 P/F SYNCHRONOUS PRESETTABLE 4-BIT COUNTER TC40H160 TC40H161 TC40H162 TC40H163 DECADE. BINARY. DECADE. BINARY. ASYNCHRONOUS
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TC40H160P/F
H162P/F
JC40H161
P/F-TC40H163P/F
TC40H160
TC40H161
TC40H162
TC40H163
TC40H160/161/162/163
TC40H160/162
TC40H161P
TC40H160P
tc40h182
TC40H161P/F-
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fuse code Jd 0,7A
Abstract: odv marking PM5323 PM5344 PM5361 PM5371 TU12
Text: S tan d a r d PM I / I P roduct _ _ _ PRELIMINARY INFORMATION P M C -S ie rra , Inc. PM5361 TUPP SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FEA TU R ES • Configurable, multi-channel, payload processor for alignment of SONET virtual tributaries VTs or SDH tributary units (TUs). Processes an STS-3 or STM-1 byte
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PM5361
920526S7
920102S8
0GD2447
fuse code Jd 0,7A
odv marking
PM5323
PM5344
PM5371
TU12
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NJU3715
Abstract: NJU3715G NJU3715L
Text: N J U3 7 1 5 16- BI T S E R I A L TO P A R A L L E L C O N V E R T E R • • • • • • • GENERAL DESCRIPTION The NJU3715 is a 16-bit serial to parallel converterespecial ly apply to MPU outport expander. The effective outport assignment of MPU is available
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16-BIT
NJU3715
NJU3715L
NJU3715G
Ud-9-57
P1-P16
NJU3715G
NJU3715L
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Untitled
Abstract: No abstract text available
Text: TC4028BiyBF C 2M O S DIGITAL IN T EG R A T E D CIRCUIT S ILIC O N M ON OLITH IC TC4028BP/TC4028BF BCD-TO-DECIMAL DECODER The TC4028BP/BF is a BCD-to-DECIMAL decoder which converts BCD signal into DECIMAL signal. Of ten outputs from QO to Q9, one output correspond
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TC4028BiyBF
TC4028BP/TC4028BF
TC4028BP/BF
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Untitled
Abstract: No abstract text available
Text: C 2M O S S IL IC O N TC5018P TC5018P D IG ITA L IN T E G R A T E D C IR C U IT M O N O L IT H IC 4 BIT BINARY COUNTER WITH CLOCK GENERATOR TC5018P is four digit binary counter equipped with CR oscillator circuit to automatically generate the clock pulse and RS flip-flop to provide the clock
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TC5018P
TC5018P
500kHz
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Untitled
Abstract: No abstract text available
Text: biE D ^7540 • □□saw b?s ■ tos2 C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC_ TOS H IB A TC4014BP L O G I C / M E M O R Y 8-STAGE STATIC SHIFT REGISTER (SYNCHRONOUS PARALLEL OR SERIAL INPUT/SERIAL OUTPUT) TC4014BP is 8 stage shift register having PARALLEL
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TC4014BP
TC4014BP
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A17-A14
Abstract: No abstract text available
Text: W89C940 yfTTPX S S S S S S S S S S S S S S S S S S S S S S S S S S \\\\\\ E ¡ecirosri ic s C o rp . ELANC-PCI TWISTED-PAIR ETHER-LAN CONTROLLER WITH
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W89C940
W89C902
240pF.
PE64103.
A17-A14
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MB87091
Abstract: Kv00 BUT20
Text: October 1991 Edition 1.0 FUJITSU DATA SHEET MB87091 SERIAL INPUT PLL FREQUENCY SYNTHESIZER CMOS SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH POWER SAVING FUNCTION The Fujitsu MB87091 is a CMOS serial input Phase Locked Loop PLL frequency synthesizer ideal for use in cordless telephone sets and other radio equipment. It
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MB87091
14-bit
12-bit
KV0017-91XK1
Kv00
BUT20
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AMD Confidential
Abstract: Ox41 lg lcd monitor circuit diagram free "error correction algorithm" atm with an eye block diagram
Text: r « PMC-Sierra, Inc. PMS3S0 s /u n i-u ltra datasheet PMC-960924 ISSUE 4 SATURN USER NETWORK INTERFACE PM5350 S/UNI-155-ULTRA SATURN USER NETWORK INTERFACE 155.52 & 51.84 MBIT/S DATA SHEET ISSUE 7: NOVEMBER 1997 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604.415.6000
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PMC-960924
PM5350
S/UNI-155-ULTRA
PMC-960924
PM5350
PM5350S/UNI-ULTRA
PMC-960489
AMD Confidential
Ox41
lg lcd monitor circuit diagram free
"error correction algorithm"
atm with an eye block diagram
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380 TVL cmos
Abstract: motorola idp
Text: DA TASHEET PM PMC-920525 ISSUE 5 PMC-Sierra, Inc. PM5371 t u d x SONET/SDH TRtBUTAR Y UNIT CROSS CONNECT PM5371 TUDX SONET/SDH TRIBUTARY UNIT CROSS CONNECTTELECOM DATA SHEET ISSUE 5: JULY 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-920525
PM5371
PM5371
PMC-920525
PMC-920103,
PMC-920103
380 TVL cmos
motorola idp
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Untitled
Abstract: No abstract text available
Text: KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD GENERAL DESCRIPTION The KS7212 is a CMOS integrated circuit designed for making various timing pulses for B/W CCD camera. FEATURES - Compatible with both EIA and CCIR mode EIA: KC73125(U -M, CCIR : KC73129(U)-M)
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KS7212
KS7212
KC73125
KC73129
06992MHz,
93750MHz
48-QFP-0707
GG37fl4M
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Untitled
Abstract: No abstract text available
Text: 83C94 10BASE-T TWISTED PAIR TRANSCEIVER Technology, Incorporated PRELIMINARY 1993 Features • Low Power CMOS Technology - 125 \iA Standby typical ■ High-speed receiver architecture minimizes Jitter
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83C94
10BASE-T
28-pln
8020/8023A
MD400097/B
83C94
28-pin
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TVP1510
Abstract: No abstract text available
Text: ISO-CMOS ST-BUS FAMILY MITEL* Features MT8940 T1/CEPT Digital Trunk PLL _ ISSUE 7_ July 1993 Ordering Information • • • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS
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MT8940
MT8940AC
MT8940AE
MT8940
CL-50pF
TVP1510
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