F100K
Abstract: SY100S325 SY100S325FC SY100S325FCTR SY100S325JC
Text: LOW-POWER HEX ECL-to-TTL TRANSLATOR Micrel, Inc. DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Max. propagation delay of 3.7ns IEE min. of –37mA TTL outputs Extended supply voltage option: VEE = –4.2V to –5.5V 25% faster than National's 325
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SY100S325
F100K
24-pin
28-pin
SY100S325
M9999-061306
F100K
SY100S325FC
SY100S325FCTR
SY100S325JC
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F100K
Abstract: SY100S325 SY100S325FC SY100S325JC SY100S325JCTR
Text: LOW-POWER HEX ECL-to-TTL TRANSLATOR SY100S325 DESCRIPTION FEATURES • Max. propagation delay of 3.7ns ■ IEE min. of –37mA ■ TTL outputs ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ 25% faster than National's 325 ■ Differential inputs with built-in offset
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Original
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SY100S325
F100K
24-pin
28-pin
SY100S325
generaF24-1
SY100S325JC
J28-1
SY100S325JCTR
F100K
SY100S325FC
SY100S325JC
SY100S325JCTR
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16D14
Abstract: No abstract text available
Text: LOW-POWER HEX ECL-to-TTL TRANSLATOR SY100S325 FINAL DESCRIPTION FEATURES • Max. propagation delay of 3.7ns ■ IEE min. of –37mA ■ TTL outputs ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ 25% faster than National's 325 ■ Differential inputs with built-in offset
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SY100S325
F100K
24-pin
28-pin
SY100S325
SY100S325JC
J28-1
SY100S325JCTR
16D14
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F100K
Abstract: SY100S325 SY100S325JC SY100S325JCTR
Text: LOW-POWER HEX ECL-to-TTL TRANSLATOR Micrel, Inc. DESCRIPTION FEATURES • Max. propagation delay of 3.7ns ■ IEE min. of –37mA ■ TTL outputs ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ 25% faster than National's 325 ■ Differential inputs with built-in offset
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Original
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PDF
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SY100S325
F100K
28-pin
SY100S325
M9999-051607
F100K
SY100S325JC
SY100S325JCTR
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D2418
Abstract: F100K SY100S325 SY100S325DC SY100S325FC SY100S325JC SY100S325JCTR
Text: SYNERGY LOW-POWER HEX ECL-to-TTL TRANSLATOR SEMICONDUCTOR SYNERGY SY100S325 SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES • Max. propagation delay of 3.7ns The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be
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SY100S325
SY100S325
SY100S325DC
D24-1
SY100S325FC
F24-1
SY100S325JC
J28-1
D2418
F100K
SY100S325DC
SY100S325FC
SY100S325JC
SY100S325JCTR
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Untitled
Abstract: No abstract text available
Text: ^ i.OW-POWER HEX EC!.-lo-TTL TRANSLATOR S YN ER G Y :viooS325 S E M IC O N D U C T O R D ES C R IPTIO N FE A TU R E S • Max. propagation delay of 3.7ns ■ Iee min. of -37m A ■ TTL outputs ■ Extended supply voltage option: Vee = -4.2V to -5.5V ■ 25% faster than National's 325
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SY100S325DC
SY100S325FC
SY100S325JC
SY100S325JCTR
D24-1
F24-1
J28-1
J28-1
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LD523
Abstract: No abstract text available
Text: LO W -PO W ER HEX ECL-to-TTL TRANSLATOR SYNERG Y SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 3.7ns Ie e min. o f-37 m A TTL outputs Extended supply voltage option: V ee = -4.2V to -5.5V 25% faster than National's 325 Differential inputs with built-in offset
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SY100S325
018-Mot
LD523
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Untitled
Abstract: No abstract text available
Text: LOW -PO W ER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 3.7ns T h e S Y 1 0 0 S 3 2 5 a re h e x tra n s la to rs fo r c o n v e rtin g 1 0 0 K E C L lo g ic le v e ls to T T L lo g ic le v e ls . In p u ts ca n be
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SY100S325
SY100S325DC
SY100S325FC
SY1OOS325JC
SY100S325JCTR
D24-1
F24-1
J28-1
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Untitled
Abstract: No abstract text available
Text: V LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 3.7ns Ie e The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting or differential receivers.
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SY100S325
SY100S325
75Ki2
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Untitled
Abstract: No abstract text available
Text: * LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 3.7ns The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting or differential receivers.
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OCR Scan
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SY100S325
SY100S325
75Ki2
SY100S325DC
D24-1
SY100S325FC
F24-1
SY100S325JC
J28-1
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F100K
Abstract: SY100S325 SY100S325DC SY100S325FC D2618
Text: * LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 S E M IC O N D U C TO R FEATURES DESCRIPTION I Max. propagation delay of 3.7ns I Iee min. of -37m A The S Y 100S 325 are hex tran sla to rs fo r converting 100K ECL logic levels to TTL logic levels. Inputs can be
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SY100S325
-37mA
F100K)
D24-1
SY100S325DC
D24-1
SY100S325FC
F24-1
SY100S325JC
F100K
SY100S325
D2618
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Untitled
Abstract: No abstract text available
Text: LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERG Y SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 3.7ns Iee min. o f-37 m A TTL outputs Extended supply voltage option: V ee = -4 .2 V to -5 .5 V 25% faster than National's 325 Differential inputs with built-in offset
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OCR Scan
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SY100S325
SY100S325
75Ki2
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