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    STMicroelectronics EVALSPEAR300

    SPEAR300 EVAL BRD
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    DigiKey EVALSPEAR300 Box 3 1
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    STMicroelectronics EVALSPEAR310

    SPEAR310 EVAL BRD
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    DigiKey EVALSPEAR310 Box 3 1
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    STMicroelectronics SPEAR300-2

    IC MPU SPEAR 333MHZ 289LFBGA
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    DigiKey SPEAR300-2 Tray 756
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    Verical SPEAR300-2 1,509 1
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    Arrow Electronics SPEAR300-2 1,509 99 Weeks 1
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    STMicroelectronics SPEAR600-2

    IC MPU SPEAR 333MHZ 420BGA
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    DigiKey SPEAR600-2 Tray 360
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    STMicroelectronics SPEAR600-2 1
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    STMicroelectronics SPEAR310-2

    IC MPU SPEAR 333MHZ 289LFBGA
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    SPEAR Datasheets (14)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SPEAR-07-NC03 STMicroelectronics Ethernet Communication Controller with USB-Host Original PDF
    SPEAR-09-B042 STMicroelectronics SPEAr BASIC ARM 926EJ-S core, customizable logic, large IP portfolio SoC Original PDF
    SPEAR-09-H0 STMicroelectronics SPEAr Head ARM 926, 200K customizable eASIC gates, large IP portfolio SoC Original PDF
    SPEAR-09-H022 STMicroelectronics SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC Original PDF
    SPEAR-09-H022 STMicroelectronics SPEAr Head ARM 926, 200K customizable eASIC gates, large IP portfolio SoC Original PDF
    SPEAR-09-H042 STMicroelectronics SPEAr Head200, ARM 926, 200 K customizable eASIC gates, large IP portfolio SoC Original PDF
    SPEAR-09-H122 STMicroelectronics SPEAr TM Head600 Original PDF
    SPEAR-09-H122 STMicroelectronics SPEAr Head600 Original PDF
    SPEAR-09-H122 STMicroelectronics SPEAr Head600 Original PDF
    SPEAR-09-P022 STMicroelectronics SPEAr Plus600 dual processor cores Original PDF
    SPEAR300-2 STMicroelectronics Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU ARM9 289LFBGA Original PDF
    SPEAR310-2 STMicroelectronics Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU ARM9 289LFBGA Original PDF
    SPEAR320-2 STMicroelectronics Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU ARM9 289LFBGA Original PDF
    SPEAR600-2 STMicroelectronics Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU DUAL ARM9 420PBGA Original PDF

    SPEAR Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: SPEAR-09-H020 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC DATA BRIEF Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates with 8 channels internal DMA high speed


    Original
    PDF SPEAR-09-H020 ARM926EJ-S PBGA420

    Untitled

    Abstract: No abstract text available
    Text: SPEAr1310 Dual-core Cortex A9 embedded MPU for communications Data brief Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – Supporting both symmetric SMP and asymmetric (AMP) multiprocessing – 32+32 KB L1 Instructions/Data cache per


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    PDF SPEAr1310 64-bit DDR2-800/DDR3-1066 16/32y

    wd 969 usb

    Abstract: SPEAR320-2 SD protocol SPEAr320 vxworks driver
    Text: SPEAr320 Embedded MPU with ARM926 core, optimized for factory automation and consumer applications Features • ARM926EJ-S 333 MHz core ■ High-performance 8-channel DMA ■ Dynamic power-saving features ■ Configurable peripheral functions on 102 shared I/Os.


    Original
    PDF SPEAr320 ARM926 ARM926EJ-S LPDDR-333/DDR2-666 16-bit 16bit wd 969 usb SPEAR320-2 SD protocol SPEAr320 vxworks driver

    GEIA-STD-0002-01

    Abstract: military mcm Manufacturer Logos FIPS-197
    Text: Going beyond the call of duty for military and aerospace applications Altera Enhanced COTS PLD Initiative From security to rugged operating environments and design productivity, you face unique concerns in developing military and aerospace applications. The Altera Enhanced COTS PLD Initiative spearheads development of FPGAs,


    Original
    PDF SS-01061-1 GEIA-STD-0002-01 military mcm Manufacturer Logos FIPS-197

    PH6N

    Abstract: ph5n transistor PH6n ph4n ph8n PH7n DDR2 pcb layout transistor ph4n transistor ph0n "ph4n"
    Text: AN2715 Application note IBIS models for signal integrity simulation of SPEAr600 applications Introduction This application note is intended for hardware developers that are using the SPEAr600 embedded MPU in their target design. The IBIS models are mandatory to run signal integrity simulation in the application PCB.


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    PDF AN2715 SPEAr600 SPEAr600 PH6N ph5n transistor PH6n ph4n ph8n PH7n DDR2 pcb layout transistor ph4n transistor ph0n "ph4n"

    LCD Panel Display Signal Theory

    Abstract: sharp lcd panel pin LCD Panel Theory STN colour LCD for china 14027 LQ043T1DG01 sharp lcd panel 20 pin Sharp LQ043T1DG01 SPEAr300 480x272
    Text: AN2641 Application note Using the color LCD controller CLCD in the SPEAr embedded MPU family Introduction The SPEAr embedded MPU family is family of configurable MPUs, based on the ARM926 CPU core. Several members the SPEAr MPU family have an embedded ARM PL-110 ColorLCD controller (CLCD). This Application Note describes how to configure and operate any


    Original
    PDF AN2641 ARM926 PL-110 LCD Panel Display Signal Theory sharp lcd panel pin LCD Panel Theory STN colour LCD for china 14027 LQ043T1DG01 sharp lcd panel 20 pin Sharp LQ043T1DG01 SPEAr300 480x272

    7812 TO-3

    Abstract: SPEAR310 4027 pin diagram SPEAr600 M25Pxxx LK 1628 spear3XX jtag 8bit nand flash upd programmable timer ST 7812
    Text: SPEAr310 Embedded MPU with ARM926 core, flexible memory support, extended set of powerful connectivity features Features • ARM926EJ-S 333 MHz core ■ High-performance 8-channel DMA ■ Dynamic power-saving features ■ Configurable peripheral functions multiplexed


    Original
    PDF SPEAr310 ARM926 ARM926EJ-S LPDDR-333/DDR2-666 16-bit 32bit 7812 TO-3 SPEAR310 4027 pin diagram SPEAr600 M25Pxxx LK 1628 spear3XX jtag 8bit nand flash upd programmable timer ST 7812

    Untitled

    Abstract: No abstract text available
    Text: SPEAr1310 Dual-core Cortex A9 embedded MPU for communications Data brief Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – Supporting both symmetric SMP and asymmetric (AMP) multiprocessing – 32+32 KB L1 Instructions/Data cache per


    Original
    PDF SPEAr1310 64-bit DDR2-800/DDR3-1066 16/32y

    PH6n

    Abstract: ph5n ph8n
    Text: SPEAR-09-P022 SPEAr Plus600 dual processor cores Preliminary Data Features • Dual ARM926EJ-S core @333MHz.600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool.


    Original
    PDF SPEAR-09-P022 Plus600 ARM926EJ-S 333MHz. 600KByte 128KByte 166MHz 32KByte 8/16bit 200MHz) PH6n ph5n ph8n

    ph5n

    Abstract: "ph4n" ph6n UART TTL buffer ph0n DDRDATA11 kss3k
    Text: SPEAR-09-H122 SPEAr Head600 Preliminary Data Features • ARM926EJ-S core @333MHz.600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool. ■ Multilayer AMBA 2.0 compliant Bus with fMAX


    Original
    PDF SPEAR-09-H122 Head600 ARM926EJ-S 333MHz. 600KByte 128KByte 166MHz 32KByte 8/16bit 200MHz) ph5n "ph4n" ph6n UART TTL buffer ph0n DDRDATA11 kss3k

    ARM926EJ-S

    Abstract: JESD97 LFBGA289 SPEAR-09-H022 SPEAR-09-H042 r8 u4 h1ur H042
    Text: SPEAR-09-H042 SPEAr Head200 ARM 926, 200 K customizable eASIC™ gates, large IP portfolio SoC Data Brief Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates 16K LUT equivalent with 8 channels internal


    Original
    PDF SPEAR-09-H042 Head200 ARM926EJ-S LFBGA289 JESD97 LFBGA289 SPEAR-09-H022 SPEAR-09-H042 r8 u4 h1ur H042

    transistor PH6n

    Abstract: PH6N SPEAR-09-P022 ph5n ph4n ph8n Plus600 TA 8268 analog ARM926EJS ARM926EJ-S
    Text: SPEAR-09-P022 SPEAr Plus600 dual processor cores Preliminary Data Features • Dual ARM926EJ-S core @333 MHz ■ 600 Kbyte reconfigurable logic array with 88 dedicated general purposes I/Os, 9 LVDS channels and 128 Kbyte configurable internal memory pool


    Original
    PDF SPEAR-09-P022 Plus600 ARM926EJ-S 8/16-bit transistor PH6n PH6N SPEAR-09-P022 ph5n ph4n ph8n TA 8268 analog ARM926EJS

    Untitled

    Abstract: No abstract text available
    Text: Multiformat, Multistandard Rasterizer WVR7200 Data Sheet New Tektronix-patented Spearhead display and Luma Qualified Vector LQV display facilitate precise color adjustment for post-production applications (Opt. PROD) Stereoscopic 3D Video Displays for Camera Alignment and


    Original
    PDF WVR7200 CEA708/608 STD-B35/B37/B39, TR-B22, TR-B23 2PW-27631-0

    Untitled

    Abstract: No abstract text available
    Text: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP


    Original
    PDF SPEAr1340 DDR3-1066, DDR2-1066 533MHz) 16-/32-bit,

    Untitled

    Abstract: No abstract text available
    Text: SPEAr320 Embedded MPU with ARM926 core, optimized for factory automation and consumer applications Features • ARM926EJ-S 333 MHz core ■ High-performance 8-channel DMA ■ Dynamic power-saving features ■ Configurable peripheral functions on 102 shared I/Os.


    Original
    PDF SPEAr320 ARM926 ARM926EJ-S LPDDR-333/DDR2-666 16-bit 16bit

    Netstat Commands

    Abstract: pendrive CRC32 usleep "routing tables"
    Text: UM0477 User Manual SPEAr Plus Linux SDK, embedded root filesystem Introduction This document provides information about the root filesystem for embedded applications provided with the SPEAr Plus Linux SDK, ver 1.1. The root filesystem provides the main Linux file structure accessible to user space, in


    Original
    PDF UM0477 Netstat Commands pendrive CRC32 usleep "routing tables"

    USB to ethernet bridge

    Abstract: No abstract text available
    Text: SPEAR-09-L040 SPEAr Lite ARM 946, 400K gates eASIC™, large IP portfolio SoC DATA BRIEF Features • ARM946E-S fMAX = 192MHz ■ 400K equivalent customizable gates with 123 dedicated GP I/Os ■ AMBA 2.0 compliant Bus fMAX = 96MHz ■ Clock Generator ■


    Original
    PDF SPEAR-09-L040 ARM946E-S 192MHz 96MHz PBGA568 35x35mm) USB to ethernet bridge

    H122

    Abstract: ph6n PH5N ph8n transistor PH6n ph7n ph4n ARMv5TEJ 0xE12 E31821
    Text: SPEAR-09-H122 SPEAr Head600 Preliminary Data Features • ARM926EJ-S core @333MHz.600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool. ■ Multilayer AMBA 2.0 compliant Bus with fMAX


    Original
    PDF SPEAR-09-H122 Head600 ARM926EJ-S 333MHz. 600KByte 128KByte 166MHz 32KByte 8/16bit 200MHz) H122 ph6n PH5N ph8n transistor PH6n ph7n ph4n ARMv5TEJ 0xE12 E31821

    Untitled

    Abstract: No abstract text available
    Text: Xcelite Electrician’s Knife Product Details Catalog No. K22 UPC Code 037103484239 Length 4 in./100 mm Jaw Capacity None Blade/Point Spear Point/Screw Type Driver Handle Type Delrin Industrial Packaging Box/Carton Low Res. K22_100.jpg Image High Res. K22_300.jpg


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    PDF

    pch7970

    Abstract: "Signal Conditioning" Philips MRKII
    Text: P2SC Signal Conditioning Chip family Designed for tire pressure monitoring A true world leader in RF identification technologies, NXP is spearheading the innovative use of this technology in Tire Pressure Monitoring Systems TPMS . Designed for all remote sensing


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    PDF 32-bit pch7970 "Signal Conditioning" Philips MRKII

    cortex a9 specification

    Abstract: Cortex A9 instruction set Dual-core ARM Cortex-A9 CPU spear1310 led matrix 16X32 china cortex a9 arm cortex a9 ARM v7 cortex a9 block diagram led matrix 16X32 axi compliant ddr3 controller
    Text: SPEAr1310 Dual-core Cortex A9 embedded MPU for communications Data brief Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – Supporting both symmetric SMP and asymmetric (AMP) multiprocessing – 32+32 KB L1 Instructions/Data cache per


    Original
    PDF SPEAr1310 64-bit DDR2-800/DDR3-1066 cortex a9 specification Cortex A9 instruction set Dual-core ARM Cortex-A9 CPU spear1310 led matrix 16X32 china cortex a9 arm cortex a9 ARM v7 cortex a9 block diagram led matrix 16X32 axi compliant ddr3 controller

    rev counter

    Abstract: 1699 004C
    Text: AN3140 Application note How to configure the SPEAr3xx general purpose timers GPTs Introduction This application note provides information about how to configure the general purpose timers (GPTs) integrated in the SPEAr3xx embedded MPU family. General purpose timers (GPTs) play an important role in any system as they provide a


    Original
    PDF AN3140 rev counter 1699 004C

    h044

    Abstract: SPEAr310 16862 uart baud rate spear uart baud rate spear linux SPEAr320 SPEAr300 AA19 ARM926
    Text: AN3123 Application note Using the UART interfaces in the SPEAr embedded MPU family Introduction The SPEAr embedded MPU family is a family of configurable MPUs, based on the ARM926 CPU core. Each member of the SPEAr MPU family has one or more embedded ARM PL011


    Original
    PDF AN3123 ARM926 PL011 UM0851) h044 SPEAr310 16862 uart baud rate spear uart baud rate spear linux SPEAr320 SPEAr300 AA19 ARM926

    pendrive

    Abstract: stlinux api spear 310 PENDRIVE USB how to make pendrive pendrive datasheet 10 steps flasher circuit STLinux Linux SPEAr 300
    Text: UM0844 User manual Getting started with SPEAr Linux support package LSP Introduction This manual provides application developers with a first introduction to the Linux-based reference software installed in the Flash memory of the SPEAr evaluation boards. It is not


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    PDF UM0844 pendrive stlinux api spear 310 PENDRIVE USB how to make pendrive pendrive datasheet 10 steps flasher circuit STLinux Linux SPEAr 300