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    SDRAM 4 BANK 4096 16 Search Results

    SDRAM 4 BANK 4096 16 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    707278L15PF9 Renesas Electronics Corporation Bank Switchable DP RAM Visit Renesas Electronics Corporation
    707278S12PF8 Renesas Electronics Corporation Bank Switchable DP RAM Visit Renesas Electronics Corporation
    707278S25PF9 Renesas Electronics Corporation Bank Switchable DP RAM Visit Renesas Electronics Corporation
    707288L15PFG Renesas Electronics Corporation Bank Switchable DP RAM Visit Renesas Electronics Corporation
    707288L25PF8 Renesas Electronics Corporation Bank Switchable DP RAM Visit Renesas Electronics Corporation

    SDRAM 4 BANK 4096 16 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    HYB 39S128160CT-7

    Abstract: HYB 39S128800CT-7 HYB 39S128160CT-7.5
    Text: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: -7 -7.5 -8 Units • Automatic and Controlled Precharge Command fCK 143 133 125 MHz • Data Mask for Read/Write Control (x4, x8)


    Original     		PDF 39S128400/800/160CT 128-MBit P-TSOPII-54 400mil PC100 P-TSOPII-54 GPX09039 HYB 39S128160CT-7 HYB 39S128800CT-7 HYB 39S128160CT-7.5

    EM639325TS

    Abstract: EM639325Ts-6g
    Text: EtronTech EM639325TS 4M x 32 SDRAM Preliminary Rev 0.5 May/2007 Features • • • • • • • • • • • • Clock rate: 166 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (1M x 32bit x 4bank) Programmable Mode


    Original     		PDF EM639325TS May/2007) 32bit cycles/64ms 86-Lead EM639325TS-6G 166MHz EM639325TS EM639325Ts-6g

    EM669325

    Abstract: No abstract text available
    Text: EtronTech EM669325BK 4M x 32 SDRAM Preliminary Rev 0.5 May/2007 Features • • • • Clock rate: 166 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (1M x 32bit x 4bank) Programmable Mode - CAS# Latency: 3 - Burst Length: 1, 2, 4, 8, or full page


    Original     		PDF EM669325BK May/2007) 32bit cycles/64ms 8x13mm, EM669325BK-6G 166MHz 90-FBGA, EM669325

    Untitled

    Abstract: No abstract text available
    Text: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: -7 -7.5 -8 Units • Automatic and Controlled Precharge Command fCK 143 133 125 MHz • Data Mask for Read/Write Control (x4, x8)


    Original     		PDF 39S128400/800/160CT 128-MBit

    HM5212165LTD-10

    Abstract: HM5212165TD-10 HM5212805LTD-10 HM5212805TD-10 Hitachi DSA00280
    Text: HM5212165 Series HM5212805 Series 128M LVTTL interface SDRAM 66 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank ADE-203-881B Z Rev. 1.0 Jul. 10, 1998 Description The Hitachi HM5212165 is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165 HM5212805 16-bit ADE-203-881B 128-Mbit 2097152-word HM5212165LTD-10 HM5212165TD-10 HM5212805LTD-10 HM5212805TD-10 Hitachi DSA00280

    P-TSOPII-54

    Abstract: No abstract text available
    Text: HYB 39S128400/800/160DT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM Preliminary Target Specification 10.01 High Performance: • Multiple Burst Read with Single Write Operation -6 -7 -7.5 -8 Units fCK 166 143 133 125 MHz • Automatic and Controlled Precharge


    Original     		PDF 39S128400/800/160DT 128-MBit HYB39S128400/800/160DT P-TSOPII-54

    HM5212165DLTD-10

    Abstract: HM5212165DTD-10 HM5212805DLTD-10 HM5212805DTD-10 Hitachi DSA00280
    Text: HM5212165D Series HM5212805D Series 128M LVTTL interface SDRAM 100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank ADE-203-945C Z Preliminary, Rev. 0.3 Dec. 4, 1998 Description The Hitachi HM5212165D is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165D HM5212805D 16-bit ADE-203-945C 128-Mbit 2097152-word HM5212165DLTD-10 HM5212165DTD-10 HM5212805DLTD-10 HM5212805DTD-10 Hitachi DSA00280

    hx 2272 DECODER

    Abstract: sdram 4 bank 4096 16 HM5212165LTD-10 HM5212165TD-10 HM5212805LTD-10 HM5212805TD-10 Hitachi DSA00196
    Text: HM5212165 Series HM5212805 Series 128M LVTTL interface SDRAM 66 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank ADE-203-881B Z Rev. 1.0 Jul. 10, 1998 Description The Hitachi HM5212165 is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The Hitachi


    Original     		PDF HM5212165 HM5212805 16-bit ADE-203-881B 128-Mbit 2097152-word hx 2272 DECODER sdram 4 bank 4096 16 HM5212165LTD-10 HM5212165TD-10 HM5212805LTD-10 HM5212805TD-10 Hitachi DSA00196

    PC133-333

    Abstract: P-TSOPII-54 hyb39s64400
    Text: HYB39S64400/800/160A/BT L 64MBit Synchronous DRAM Ultra High Speed 64 MBit Synchronous DRAM PC143 & PC133 • High Performance: -7 -7.5 Units fCKmax. 143 133 MHz tCK3 7 7.5 ns tAC3 5.4 5.4 ns tCK2 10 10 ns tAC2 5.5 6 ns • Fully Synchronous to Positive Clock Edge


    Original     		PDF HYB39S64400/800/160A/BT 64MBit PC143 PC133 P-TSOPII-54 400mil PC143 PC133 PC133-333 hyb39s64400

    HM5212165DLTD-10

    Abstract: sdram 4 bank 4096 16 HM5212165DTD-10 HM5212805DLTD-10 HM5212805DTD-10 Hitachi DSA00196
    Text: HM5212165D Series HM5212805D Series 128M LVTTL interface SDRAM 66 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank ADE-203-945 Z Preliminary Rev. 0.0 Aug. 4, 1998 Description The Hitachi HM5212165D is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165D HM5212805D 16-bit ADE-203-945 128-Mbit 2097152-word HM5212165DLTD-10 sdram 4 bank 4096 16 HM5212165DTD-10 HM5212805DLTD-10 HM5212805DTD-10 Hitachi DSA00196

    953b

    Abstract: 953B IC HX 2272 HM5212165DLTD-B60 HM5212165DTD-B60 HM5212805DTD-B60 ADE-203-953B HM5212165D-B60 Hitachi DSA00243
    Text: HM5212165D-B60 HM5212805D-B60 128M LVTTL interface SDRAM 100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/100 SDRAM ADE-203-953B Z Preliminary, Rev. 0.2 Nov. 30, 1998 Description The Hitachi HM5212165D is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165D-B60 HM5212805D-B60 16-bit PC/100 ADE-203-953B HM5212165D 128-Mbit 2097152-word HM5212805D 953b 953B IC HX 2272 HM5212165DLTD-B60 HM5212165DTD-B60 HM5212805DTD-B60 ADE-203-953B HM5212165D-B60 Hitachi DSA00243

    Hitachi DSA002753

    Abstract: No abstract text available
    Text: HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 [ 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1048 Z Preliminary Rev. 0.0 May. 17, 1999 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The Hitachi HM5212805F is a 128-Mbit SDRAM organized as 4194304-word × 8-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.


    Original     		PDF HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 Hz/100 16-bit PC/133, PC/100 ADE-203-1048 HM5212165F 128-Mbit 2097152-word Hitachi DSA002753

    HM5212165DLTD-A60

    Abstract: HM5212165DTD-A60 HM5212805DTD-A60 Hitachi DSA00280 DSA0028092.
    Text: HM5212165D-A60 HM5212805D-A60 128M LVTTL interface SDRAM 100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/100 SDRAM ADE-203-987 Z Preliminary, Rev. 0.0 Nov. 30, 1998 Description The Hitachi HM5212165D is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165D-A60 HM5212805D-A60 16-bit PC/100 ADE-203-987 HM5212165D 128-Mbit 2097152-word HM5212805D HM5212165DLTD-A60 HM5212165DTD-A60 HM5212805DTD-A60 Hitachi DSA00280 DSA0028092.

    smd marking T22

    Abstract: PC133-222-520
    Text: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • High Performance: • Multiple Burst Read with Single Write Operation -7 -7.5 -8 Units fCK 143 133 125 MHz • Automatic and Controlled Precharge Command tCK3 7 7.5 8 ns • Data Mask for Read/Write Control (x4, x8)


    Original     		PDF 39S128400/800/160CT 128-MBit smd marking T22 PC133-222-520

    HM5212805F-75A

    Abstract: PC133-SDRAM Hitachi DSA00164 HM5212165F-75A
    Text: HM5212165F-75A HM5212805F-75A 128M LVTTL interface SDRAM 133 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133 SDRAM ADE-203-1049 Z Preliminary Rev. 0.0 May. 20, 1999 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The Hitachi HM5212805F is a 128-Mbit SDRAM organized as 4194304-word × 8-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.


    Original     		PDF HM5212165F-75A HM5212805F-75A 16-bit PC/133 ADE-203-1049 HM5212165F 128-Mbit 2097152-word HM5212805F HM5212805F-75A PC133-SDRAM Hitachi DSA00164 HM5212165F-75A

    a60 GENERATOR

    Abstract: Hitachi DSA00164
    Text: HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1048A Z Rev. 1.0 Jan. 31, 2000 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 Hz/100 16-bit PC/133, PC/100 ADE-203-1048A HM5212165F 128-Mbit 2097152-word a60 GENERATOR Hitachi DSA00164

    Untitled

    Abstract: No abstract text available
    Text: HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1048A Z Rev. 1.0 Jan. 31, 2000 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 Hz/100 16-bit PC/133, PC/100 ADE-203-1048A HM5212165F 128-Mbit 2097152-word

    HM5212165F

    Abstract: HM5212165FTD-75 HM5212165FTD-A60
    Text: HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1048A Z Rev. 1.0 Jan. 31, 2000 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 Hz/100 16-bit PC/133, PC/100 ADE-203-1048A HM5212165F 128-Mbit 2097152-word HM5212165FTD-75 HM5212165FTD-A60

    Untitled

    Abstract: No abstract text available
    Text: HM5212165FLTD-75/A60/B60 HM5212805FLTD-75/A60/B60 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM E0180H10 Ver. 1.0 Jul. 17, 2001 Description The HM5212165FL is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165FLTD-75/A60/B60 HM5212805FLTD-75/A60/B60 Hz/100 16-bit PC/133, PC/100 E0180H10 HM5212165FL 128-Mbit 2097152-word

    Hitachi DSA00174

    Abstract: No abstract text available
    Text: HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1048 Z Preliminary Rev. 0.0 May. 17, 1999 Description The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The


    Original     		PDF HM5212165F-75/A60/B60 HM5212805F-75/A60/B60 Hz/100 16-bit PC/133, PC/100 ADE-203-1048 HM5212165F 128-Mbit 2097152-word Hitachi DSA00174

    Untitled

    Abstract: No abstract text available
    Text: HM5212165FTD-75/A60/B60 HM5212805FTD-75/A60/B60 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM E0179H10 Ver. 1.0 Jul. 16, 2001 Description The HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The HM5212805F


    Original     		PDF HM5212165FTD-75/A60/B60 HM5212805FTD-75/A60/B60 Hz/100 16-bit PC/133, PC/100 E0179H10 HM5212165F 128-Mbit 2097152-word

    P-TSOPII-54

    Abstract: PC133 registered reference design
    Text: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • High Performance: • Multiple Burst Read with Single Write Operation -7 -7.5 -8 Units fCK 143 133 125 MHz • Automatic and Controlled Precharge Command tCK3 7 7.5 8 ns • Data Mask for Read/Write Control (x4, x8)


    Original     		PDF 39S128400/800/160CT 128-MBit P-TSOPII-54 PC133 registered reference design

    smd marking T22

    Abstract: smd transistor marking ba 128M-BIT P-TSOPII-54 P-TSOP-54 PC133 registered reference design 128-MBIT
    Text: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: -7 -7.5 -8 Units • Automatic and Controlled Precharge Command fCK 143 133 125 MHz • Data Mask for Read/Write Control (x4, x8)


    Original     		PDF 39S128400/800/160CT 128-MBit smd marking T22 smd transistor marking ba 128M-BIT P-TSOPII-54 P-TSOP-54 PC133 registered reference design

    P-TSOPII-54

    Abstract: caz smd PC133 registered reference design
    Text: HYB 39S64400/800/160ET L 64-MBit Synchronous DRAM 64-MBit Synchronous DRAM Preliminary Datasheet • Automatic and Controlled Precharge Command • High Performance: -7 -7.5 -8 Units fCKMAX 143 133 125 MHz tCK3 7 7.5 8 ns tAC3 5.4 5.4 6 ns tCK2 7.5 10 10


    Original     		PDF 39S64400/800/160ET 64-MBit P-TSOPII-54 caz smd PC133 registered reference design