A54SXA
Abstract: A54SX-A PD30111 A54SX16A
Text: v3.0 CorePCI Target, Master, and Master/Target Pr od uc t S um m ary In t e n d e d U s e • High-Performance PCI Applications Mac ro Ve ri fica ti on and Com p li ance • Actel-Developed Test Bench • Hardware Tested – Target, Master, and Master/Target, which includes
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64-Bit
A54SXA
A54SX-A
PD30111
A54SX16A
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s-master digital amplifier
Abstract: PWM 1kHz 12.288M 384M M65881AFP S-Master 3 phase sine wave pwm c source code
Text: M65881AFP REJ03F0004-0100Z Rev.1.00 2003.05.08 Digital Amplifier Processor of S-Master* Technology DESCRIPTION The M65881AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal to high precise switching-pulse digital output without analog processing.
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M65881AFP
REJ03F0004-0100Z
M65881AFP
24bit
32KHz
192KHz
s-master digital amplifier
PWM 1kHz
12.288M
384M
S-Master
3 phase sine wave pwm c source code
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s-master digital amplifier
Abstract: M65817AFP S-Master DSD128 M65818AFP sacd
Text: M65818AFP Digital Amplifier Processor of S-Master* Technology REJ03F0019-0100Z Rev.1.00 Sep.04.2003 Description The M65818AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal to high precise switching-pulse digital output without analog processing.
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M65818AFP
REJ03F0019-0100Z
M65818AFP
24bit
32KHz
192KHz
s-master digital amplifier
M65817AFP
S-Master
DSD128
sacd
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s-master digital amplifier
Abstract: 7374 s-master M65817AFP DSD64Fs DSD64 OUTR21 S-Master Processor
Text: MITSUBISHI SOUND PROCESSOR ICs M65817AFP Digital Amplifier Processor of S-Master* Technology DESCRIPTION The M65817AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal to high precise switching-pulse digital output without analog signal.The M65817AFP has built-in 24bit sampling rate converter and
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M65817AFP
M65817AFP
24bit
32KHz
192KHz
s-master digital amplifier
7374
s-master
DSD64Fs
DSD64
OUTR21
S-Master Processor
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0x1113
Abstract: No abstract text available
Text: PSoC Creator Component Data Sheet Serial Peripheral Interface SPI Master 2.0 Features • 2- to 16-bit data width • 4 SPI operating modes • Data rates to 33 Mb/s General Description The SPI Master component provides an industry-standard 4-wire master SPI interface, as well
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16-bit
0x1113
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IDT70V27
Abstract: 70V27 A14L IDT70V27S cea h12
Text: HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ IDT70V27 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave
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IDT70V27
100-pin
108-pin
144-pin
70V27
A14L
IDT70V27S
cea h12
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QL5032
Abstract: pci to dual port ram interface
Text: QL5032-QuickPCI ESP 33MHz/32-bit PCI Controller with Embedded Programmable Logic and Dual Port SRAM • • • • • High Performance PCI Controller 32-bit / 33 MHz Master/Target PCI Controller Zero-wait state PCI Master provides 132 MB/s transfer rates
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QL5032-QuickPCI
33MHz/32-bit
32-bit
95/98/NT4
64-deep
128-deep
256-deep
QL5032
QL5032
pci to dual port ram interface
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PB256C
Abstract: vhdl code for flip-flop PB256 PCI32 PQ208 QL5032 QL5032-33 "ESP"
Text: QL5032-33 - QuickPCI ESP 33 MHz/32-bit PCI Controller with Embedded Programmable Logic and Dual Port SRAM Updated: 29-Apr-99 DEVICE HIGHLIGHTS High Performance PCI Controller - 32-bit / 33 MHz Master/Target PCI Controller Zero-wait state PCI Master provides 132 MB/s transfer rates
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QL5032-33
Hz/32-bit
29-Apr-99
32-bit
95/98/NT4
PB256C
vhdl code for flip-flop
PB256
PCI32
PQ208
QL5032
"ESP"
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Untitled
Abstract: No abstract text available
Text: SC A N S TA 101 SCANSTA101 Low Voltage IEEE 1149.1 System Test Access STA Master Te x a s In s t r u m e n t s Literature Number: SNLS057I t) a l SCANSTA101 Sem iconductor Low Voltage IEEE 1149.1 System Test Access (STA) Master General Description Features
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SCANSTA101
SNLS057I
SCANSTA101
SCANPSC100.
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Untitled
Abstract: No abstract text available
Text: PCI 9060ES j e cT T T T S T T ^T T November 1995 VERSION 1.0 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General Description PCI Bus Master and Bus Slave transfers up to 132 megabytes/sec supporting three architectures: - PCI Direct Master adapter
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9060ES
200ns
250ns
300ns
LAJ31
A31-39
PCI9060ES
PCI9060ES
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93CS56
Abstract: doorbell ID l960 pci9080 9060ES 93C06 NM93CS06 NM93CS46 PCI9060ES doorbell
Text: PCI 9060ES T e c T T T T S T T ^ T T November 1995 VERSION 1.0 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General Description PCI Bus Master and Bus Slave transfers up to 132 megabytes/sec supporting three architectures: - PCI Direct Master adapter
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9060ES
200ns
250ns
300ns
1100ns
150ns
200ns
1250ns
350ns
93CS56
doorbell ID
l960
pci9080
9060ES
93C06
NM93CS06
NM93CS46
PCI9060ES
doorbell
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Untitled
Abstract: No abstract text available
Text: V962PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between Intel ¡960 Cx/Hx processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation
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V962PBC
234SG
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Untitled
Abstract: No abstract text available
Text: V292PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between AMD’s Am29030/ 40 processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation
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V292PBC
Am29030/
234SG
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Sonic DP83932
Abstract: an 9010 9010 83932 9010 plx DP83932 EISA Sonic Drive
Text: 32E D P L X TECHNOLOGY CORP b û S S m i 0000133 1 BIPLX T-52-33-55 EISA 9010 EISA Bus Master Interface Chip for National SONIC DP83932 LAN Controller Preliminary December 1990 Features_ _ EISA bus master interface for National DP83932 Ethernet Controller
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DP83932
T-52-33-55
128-pin
014ip
Sonic DP83932
an 9010
9010
83932
9010 plx
EISA
Sonic Drive
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Untitled
Abstract: No abstract text available
Text: \y HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L Integrated Devi ce Technology, Inc. FEATURES: more using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Interrupt Flag
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IDT7007S/L
68-pin
64-pin
MIL-STD-883,
80-pin
PN80-1)
68-pln
G68-1)
J68-1)
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Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM PRELIMINARY IDT7008S/L Integrated Device Technology, Inc. FEATURES: • • • • • more using the Master/Slave select when cascading more than one device M/S = V ih for BUSY output flag on Master, M /S = V n for BUSY input on Slave
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IDT7008S/L
84-pin
100-pin
MIL-STD-883,
100-pin
G84-1)
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Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 8 K x 16 DUAL-PORT STATIC RAM F eatures IDT7025 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device_ M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag
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IDT7025
84-pin
100-pin
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Shared resource arbitration
Abstract: No abstract text available
Text: miMHS PRELIMINARY March 1994 L 67005 DATA SHEET 8 KX 8 CMOS DUAL PORT RAM 3.3 VOLT FEATURES VERSATILE PIN SELECT FOR MASTER OR SLAVE: - M/S= H FOR BUSY OUTPUT FLAG ON MASTER - M/S = L FOR BUSY INPUT FLAG ON SLAVE INT FLAG FOR PORT TO PORT COMMUNICATION FULL HARDWARE SUPPORT OF SEMAPHORE
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7005V
6700Sffiev
hfl45b
Shared resource arbitration
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Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 1 6 K X 9 DUAL-PORT STATIC RAM Features * * * using the Master/Slave select when cascading more than one d e v i c e _ M/S = V ih fo r BUSY output flag on Master M/S = V il fo r BUSY input on Slave Busy and Interrupt Flag On-chip port arbitration logic
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20/25/35ns
68-pin
80pin
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Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 16Kx 16 DUAL-PORT STATIC RAM IDT7026S/L Integrated D e vic e Techn olo gy, Inc. multiplexed bus compatibility IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = H for B U S Y output flag on Master,
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IDT7026S/L
IDT7026
84-pin
MIL-STD-883,
G84-3)
J84-1)
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Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM FEATURES: IDT7025S/L more using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling
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20/25/35/55/70ns
15/17/20/25/35/55ns
IDT7025S
750mW
IDT7025L
IDT7025
IDT7025S/L
IL-STD-883,
100-pin
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Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 1 6 K X 9 DUAL-PORT STATIC RAM ID T 7 0 1 6 S /L Features using the Master/Slave select when cascading more than * True Dual-Ported memory cells which allow sim ultaneous one d e v i c e _ reads of the sam e memory location M/S = V ih for B U S Y output flag on Master
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20125135ns
12/15/20/25/35ns
IDT7016S
750mW
IDT70161-
68-pin
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82358
Abstract: XC96 8251 intel microcontroller architecture F245B intel 82358 INTERFACING OF 8272 WITH 8086 EISA chip set 82355 ta 8271 hq intel 82355
Text: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed fo r use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 M b ytes/S ec Maximum Data
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32-Bit
24-Byte
2L17S
82358
XC96
8251 intel microcontroller architecture
F245B
intel 82358
INTERFACING OF 8272 WITH 8086
EISA chip set
82355
ta 8271 hq
intel 82355
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A54SX72
Abstract: No abstract text available
Text: ^ c te l P r e lim in a r y v1„0 CorePCI Target+DMA Master 33/66MHz P ro d u ct S um m ary Section In te n d e d U s e • High-Performance 33MHz or 66MHz PCI Target+DMA Master Applications Page I/O Signal Descriptions 415 Supported Comm ands 418 Device Utilization
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33/66MHz
33MHz
66MHz
32-Bit,
33MHz,
66MHz,
A54SX72
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