74F401
Abstract: 74F401PC 74F401SC CRC-12 CRC-16 M14A MS-001 N14A CRC 9401
Text: Revised August 1999 74F401 CRC Generator/Checker General Description Features The 74F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials
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74F401
74F401
CRC-16
74F401PC
74F401SC
CRC-12
M14A
MS-001
N14A
CRC 9401
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g3d0
Abstract: PLCC 68 intel package dimensions "7 Bit Shift Register" data scrambler reference signal every symbols STEL-5268 2040a convolutional scrambler satellite v.35
Text: STEL-2040A Data Sheet STEL-2040A Convolutional Encoder Viterbi Decoder R FEATURES • Constraint Length 7 ■ Coding Gain of 5.2 dB @ 10-5 BER, Rate 1/2 ■ Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured) ■ Industry Standard Polynomials ■ Built in BER Monitor
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STEL-2040A
68-pin
70301A
g3d0
PLCC 68 intel package dimensions
"7 Bit Shift Register"
data scrambler
reference signal every symbols
STEL-5268
2040a
convolutional
scrambler satellite v.35
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AT91SAM
Abstract: atmel 214
Text: Features • Provides Hardware Acceleration for determining roots of polynomials defined over a finite field • Programmable Finite Field GF 2^13 or GF(2^14) • Finds Roots of Error Locator Polynomial • Programmable Number of Roots 1. Description The PMECC Error Location Controller provides hardware acceleration for determining
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11039AS
22-Feb-10
AT91SAM
atmel 214
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Convolutional Encoder
Abstract: ispLEVER project Navigator Convolutional encoder verilog coding Convolutional Puncturing Pattern digital clock project Convolutional decoder polynomial Viterbi Decoder ispLEVER project Navigator route place
Text: Convolutional Encoder User’s Guide April 2003 ipug03_02 Lattice Semiconductor Convolutional Encoder User’s Guide Introduction Lattice’s Convolutional Encoder core is a parameterizable core for convolutional encoding of a continuous input data stream. The core allows variable code rates, constraint lengths and generator polynomials. The core also supports puncturing. Puncturing enables a large range of transmission rates and reduces the bandwidth requirement
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ipug03
1-800-LATTICE
Convolutional Encoder
ispLEVER project Navigator
Convolutional
encoder verilog coding
Convolutional Puncturing Pattern
digital clock project
Convolutional decoder
polynomial
Viterbi Decoder
ispLEVER project Navigator route place
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LFSR
Abstract: c code 4 bit LFSR AN4400 code 4 bit LFSR polynomials code 24 bit LFSR simple LFSR polynomial APP4400 pseudo random numbers using lfsr
Text: Maxim > App Notes > General engineering topics Microcontrollers Keywords: microcontroller microprocessor LFSR random Jun 30, 2010 APPLICATION NOTE 4400 Pseudo random number generation using linear feedback shift registers By: Conrad Schlundt Abstract: Linear feedback shift registers are introduced along with the polynomials that completely describe them. The application note
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0x1CDDF40E
0xE6EFA07
0x29D1E9EB
0x3D391D1E
0x269FAEAC
0x47762392
0x23BB11C9
0x6B864A07
0xB4BCD35C
LFSR
c code 4 bit LFSR
AN4400
code 4 bit LFSR
polynomials
code 24 bit LFSR
simple LFSR
polynomial
APP4400
pseudo random numbers using lfsr
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RAID-5
Abstract: 440SP 440S PPC440 amcc 440 POWERPC-440SP
Text: PRODUCT BRIEF RAID 5/6 with PowerPC440SP/SPe High performance RAID computations with PowerPC 440S series Features • Hardware support for RAID 5 and RAID 6 calculations • PPC 440SPe+ supports polynomials 11d, 14d, and 30 others • PPC 440SP+ supports 14d
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PowerPC440SP/SPe
440SPe+
440SP+
POWERPC440SP/SPe
RAID-5
440SP
440S
PPC440
amcc 440
POWERPC-440SP
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Untitled
Abstract: No abstract text available
Text: ITS-90 Thermocouple Direct & Inverse Polynomials Direct Polynomials provide the thermoelectric voltage µV from a known temperature (°C); Inverse Polynomials provide the temperature (°C) from a known thermoelectric voltage (µV). Type J Thermocouples - coefficients, ci, of reference
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ITS-90
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74F402
Abstract: "XOR Gates" 54F402DM 54F402FM 54F402LM 74F402PC CRC-16 F402 J16A N16E
Text: 74F402 Serial Data Polynomial Generator/Checker General Description Features The ’F402 expandable Serial Data Polynomial generator/ checker is an expandable version of the ’F401. It provides an advanced tool for the implementation of the most widely used error detection scheme in serial digital handling systems. A 4-bit control input selects one-of-six generator polynomials. The list of polynomials includes CRC-16,
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74F402
CRC-16,
74F402
"XOR Gates"
54F402DM
54F402FM
54F402LM
74F402PC
CRC-16
F402
J16A
N16E
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Untitled
Abstract: No abstract text available
Text: ispLever CORE TM Viterbi Decoder User’s Guide October 2005 ipug04_02.0 Lattice Semiconductor Viterbi Decoder User’s Guide Introduction Lattice’s Viterbi Decoder core is a parameterizable core for decoding different combinations of convolutionally encoded sequences. The decoder core supports various code rates, constraint lengths and generator polynomials.
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ipug04
LFX1200B,
FE680,
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scrambler satellite v.35
Abstract: scrambler v.35 algorithm branch metric g1d1 sm2c convolutional G3N1 IESS-308 sCRAMBLER
Text: STEL-2050A Data Sheet STEL-2050A Convolutional Encoder Viterbi Decoder R FEATURES • Constraint Length 7 ■ Coding Gain of 5.2 dB @ 10-5 BER, Rate 1/2 ■ Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured) ■ Industry Standard Polynomials ■ Built in BER Monitor
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STEL-2050A
28-pin
scrambler satellite v.35
scrambler v.35 algorithm
branch metric
g1d1
sm2c
convolutional
G3N1
IESS-308 sCRAMBLER
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STEL-5269 512
Abstract: AN 5269 qpsk transmitter STEL-5269 74HC74 decoder STEL-5268 convolutional convolutional encoder interleaving bpsk modulator STEL-5269+512
Text: STEL-5269+512 Data Sheet STEL-5269+512 Convolutional Encoder Viterbi Decoder R FEATURES • CONSTRAINT LENGTH 7 ■ CODING RATES 1/2 AND 1/3 ■ THREE BIT SOFT-DECISION INPUTS IN ■ CODING GAIN OF 6.0 dB AT 10–5 BER, RATE 1/3 ■ INDUSTRY STANDARD POLYNOMIALS
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STEL-5269
STEL-5269 512
AN 5269
qpsk transmitter
74HC74 decoder
STEL-5268
convolutional
convolutional encoder interleaving
bpsk modulator
STEL-5269+512
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branch metric
Abstract: Viterbi Decoder viterbi algorithm branch metric report trellis 5/6 decoder Viterbi Trellis Decoder texas DSP56300 DSP56600 IS-136 Convolutional decoder
Text: Implementing Viterbi Decoders Using the VSL Instruction on DSP Families DSP56300 and DSP56600 by Dana Taipale This application report describes how to generate, from a set of convolutional code polynomials, the assembly code needed for implementation of a Viterbi decoder.
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DSP56300
DSP56600
APR40/D
branch metric
Viterbi Decoder
viterbi algorithm
branch metric report
trellis 5/6 decoder
Viterbi Trellis Decoder texas
DSP56600
IS-136
Convolutional decoder
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Reed-Solomon encoder algorithm
Abstract: LFX125B-04F256C LFX125B04F256C polynomials OC192 x8 encoder
Text: Reed-Solomon Encoder April 2003 IP Data Sheet Features General Description • 3- to 12-Bit Symbol Width ■ Configurable Polynomials Reed-Solomon codes are used to perform Forward Error Correction FEC . FEC introduces redundancy in the data before it is transmitted. The redundant data
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12-Bit
OC-192)
OC192
Reed-Solomon encoder algorithm
LFX125B-04F256C
LFX125B04F256C
polynomials
OC192
x8 encoder
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branch metric
Abstract: Viterbi Decoder Viterbi Trellis Decoder Viterbi Trellis Decoder texas DSP56300 DSP56600 IS-136
Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. Implementing Viterbi Decoders Using the VSL Instruction on DSP Families DSP56300 and DSP56600 by Dana Taipale This application report describes how to generate, from a set of convolutional code polynomials, the assembly code needed for
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DSP56300
DSP56600
APR40/D
branch metric
Viterbi Decoder
Viterbi Trellis Decoder
Viterbi Trellis Decoder texas
DSP56600
IS-136
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Untitled
Abstract: No abstract text available
Text: TMS320TCI100 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS218H − MAY 2003 − REVISED JUNE 2006 D Highest-Performance Fixed-Point Digital D D D D D Signal Processors DSPs − 1.67-, 1.39-ns Instruction Cycle Time − 600-, 720-MHz Clock Rate − Eight 32-Bit Instructions/Cycle
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TMS320TCI100
SPRS218H
39-ns
720-MHz
32-Bit
TCI100/C6416
TMS320C64x
32-/40-Bit)
32-Bit,
16-Bit,
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atxmega128B
Abstract: 141-003 0x0D00 XMEGA Application Notes
Text: 8/16-bit Atmel XMEGA B1 Microcontroller ATxmega128B1; ATxmega64B1 Features High-performance, low-power Atmel AVR® XMEGA® 8/16-bit Microcontroller Nonvolatile program and data memories 64K - 128KBytes of in-system self-programmable flash
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8/16-bit
ATxmega128B1;
ATxmega64B1
128KBytes
16-bit
atxmega128B
141-003
0x0D00
XMEGA Application Notes
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Untitled
Abstract: No abstract text available
Text: Semico n d u August 1995 t o r 74F401 CRC Generator/Checker General Description Features The ’F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in
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74F401
CRC-16
inpu34
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Untitled
Abstract: No abstract text available
Text: National Semiconductor 54F/74F401 CRC Generator/Checker General Description Features The ’F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in
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54F/74F401
CRC-16
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Untitled
Abstract: No abstract text available
Text: ¿/M iö SiBER 673480 Single Burst Error Recovery 1C Features/B enefits Ordering Inform ation • 15 MHz data rate PART NUMBER PACKAGE TEMPERATURE 673480 J C om • Selectable CRC or ECC polynomials • Standard 16-bit CRC-CCITT polynomial delects errors
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16-bit
32-bit
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Untitled
Abstract: No abstract text available
Text: tß Semiconductor National 74F401 CRC Generator/Checker General Description Features The ’F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for Implementing the most widely used error detection scheme In serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in
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74F401
CRC-16
b501122
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CRC 9401
Abstract: 311 pin diagram
Text: 401 54F/74F401 Connection Diagrams CRC Generator/Checker c p fT Z iN c c W | er p t r la Redundancy Check CRC Generator/Checker provides an lementing the most widely used error detection I data handling systems. A 3-bit control input 'g e n g jm j^ polynomials. The list of polynomials in
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54F/74F401
54F/74F
CRC 9401
311 pin diagram
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Untitled
Abstract: No abstract text available
Text: & National Semiconductor 74F401 CRC Generator/Checker General Description Features The 'F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in
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74F401
CRC-16
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scrambler satellite v.35
Abstract: IESS-308 sCRAMBLER BUS13r iess-309 standard BPSK demodulator bpsk modulation and demodulation scrambler v.35 diagram intelsat scrambler IESS309
Text: PMC r PM7018 RPFEC ERROR CORRECTION CIRCUIT DATA SHEET FEATURES • Constraint length 7 convolutional encoder polynomials 133,171 • Vrterbi decoder with up to 3 bit soft decision inputs and an 80 stage trellis • Two versions for operation at the following information data rates:
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PM7018-256
PM7018-2500
861029R5
scrambler satellite v.35
IESS-308 sCRAMBLER
BUS13r
iess-309 standard
BPSK demodulator
bpsk modulation and demodulation
scrambler v.35 diagram
intelsat scrambler
IESS309
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Untitled
Abstract: No abstract text available
Text: SiBER 673480 Single Burst Error Recovery 1C O rdering Inform ation F eatu res/ Benefits • 15 MHz data rate PART NUMBER PACKAGE TEMPERATURE 673480 J Com • Selectable CRC or ECC polynomials • Standard 16-blt CRC-CCITT polynomial detects errors • Computer-generated 32-bit ECC polynomial exceeds the
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16-bit
32-bft
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