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    Woodhead Molex 19267-0187 (ALTERNATE: PF-1/4-4CL)

    1/4 INCH HST CLEAR (LG 500 FT SPOOL) | Molex Woodhead/Brad 19267-0187
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    RS 19267-0187 (ALTERNATE: PF-1/4-4CL) Bulk 500
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    QuickLogic Corporation QL4016-0PF144C-4323

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    Bristol Electronics QL4016-0PF144C-4323 23
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    QuickLogic Corporation QL2005-OPF144C

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    Bristol Electronics QL2005-OPF144C 5
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    QuickLogic Corporation QL24X32B-2PF144C

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    Bristol Electronics QL24X32B-2PF144C 5
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    QuickLogic Corporation QL3012-0PF144C

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    Bristol Electronics QL3012-0PF144C 4
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    PF144C Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    81c78

    Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
    Text: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M


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    PDF 2147-35C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35M 2148-45C 81c78 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference

    Eclipse II Errata

    Abstract: eclipse ii PQ208 PT280 QL8025 QL8050 QL8150 QL8250 QL8325 ql8325-6
    Text: Eclipse II Devices Errata • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM This document identifies all known bugs for the Eclipse II family devices as of the date printed at the end of this document. Each issue is numbered, named and tracked individually. A severity level is also


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    Untitled

    Abstract: No abstract text available
    Text: QL3012 / QL3 0 1 2 R 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA . 12,000 usable PLD gates, 118 I/O pins 11,520 bit RAM Option E High Performance and High Density -12,000 Usable PLD Gates with 118 I/Os


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    PDF QL3012 -16-bit

    Untitled

    Abstract: No abstract text available
    Text: QL16x24B Wildcat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev A pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. B High Usable Density - A 16-by-24 array of384 logic cells provides 12,000


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    PDF QL16x24B 16-by-24 of384 84pin 100-pin 144-pin 160pin 16-bit

    TMS 4016 pin diagram

    Abstract: 4016(RAM) pin diagram of ic 4016
    Text: QL4016 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM Last Updated: April 12, 1999 QuickRAM HIGHLIGHTS . 16,000 usable PLD gates, 1181/0 pins B High Performance and High Density - 16,000 Usable PLD Gates with 118 I/Os


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    PDF QL4016 16-bit 152-bit QL4016 TMS 4016 pin diagram 4016(RAM) pin diagram of ic 4016

    CPGA144

    Abstract: No abstract text available
    Text: QL16X24B pASIC 1 FAMILY Very-High-Speed 4K 12K Gate CMOS FPGA PRELIMINARY DATA pASIC HIGHLIGHTS .4000 usable gates, 122 input pins B Very High Speed - ViaLink metal-to-metal programmable-via anti­ fuse technology, allows data path speeds over 150 MHz, and logic cell


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    PDF QL16X24B 16-by-24 QL16x24B QL16x24 CPGA144

    Untitled

    Abstract: No abstract text available
    Text: QL24X32B W ildcat 8000 Very-High-Speed 8K 24K Gate CMOS FPGA .8000 usable gates, 180 I/O pins B V ery H igh S p eed - V ia L in k m etal-to-m etal p ro g ra m m a b le-v ia antifuse technology, allow s c o u n ter speeds o v er 15 0 M H z and logic cell


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    PDF QL24X32B 24-by-32 144pin 208-pin 24x32B PQ208 M/883C MIL-STD-883D PF144 144-pin

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    Abstract: No abstract text available
    Text: QL16x24B/QL16x24BH W ildcat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B P Very High Speed - V ia L in k inetal-to-metal programmable-via anti­ fuse technology, allows counter speeds over 150 M H z and logic cell delays of under 2 ns. d .4000


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    PDF QL16x24B/QL16x24BH 16-by-24 84pin 100-pin 144-pin 144-pinCPGA, 160pin 16-bit 16x24B-l

    Untitled

    Abstract: No abstract text available
    Text: Q L16X24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


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    PDF L16X24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B PF144C

    PL84C

    Abstract: CPGA Package Diagram TQFP 10 10
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


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    PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B PF144C PL84C CPGA Package Diagram TQFP 10 10

    Untitled

    Abstract: No abstract text available
    Text: QL3012 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 pASIC 3 HIGHLIGHTS . 12,000 usable PLD gates, 1181/0 pins S High Performance and High Density -12,000 Usable PLD Gates with 118 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz


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    PDF QL3012 -16-bit

    144pin asic

    Abstract: PQ208 QL24X32B QL24X32B-1PQ208C
    Text: QL24X32B WildCaì 8000 Very-High-Speed 8K 24K Gate CMOS FPGA pASIC HIGHLIGHTS .8000 usable gates, 180 I/O pins 52 Very High Speed — ViaLink metal-to-metal programmable—via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


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    PDF QL24X32B 24-by-32 of768 144-pin 208-pin 24x32B PQ208 M/883C MIL-STD-883D 144pin asic QL24X32B-1PQ208C