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    OF OPTICAL FPGAS Search Results

    OF OPTICAL FPGAS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TLP3475W Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output), 60 V/0.4 A, 300 Vrms, WSON4 Visit Toshiba Electronic Devices & Storage Corporation
    TLP3406SRH4 Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 30 V/0.9 A, 300 Vrms, S-VSON16T Visit Toshiba Electronic Devices & Storage Corporation
    TLP5702H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TLP3407SRA Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/1 A, 500 Vrms, S-VSON4T Visit Toshiba Electronic Devices & Storage Corporation
    TLP3407SRH Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/1 A, 500 Vrms, S-VSON4T Visit Toshiba Electronic Devices & Storage Corporation

    OF OPTICAL FPGAS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    FLEX10K20

    Abstract: No abstract text available
    Text: SONET Interrupt Controller Introduction Overview SONET Synchronous Optical Network is a standard for transmission of data over optical fiber. The SONET format allows different types of formats to be transmitted over the same fiber optic line. The ispLSI 8840 is used in the port shelf section of the


    Original     		PDF Flex10K20RB240-4 Flex10K20. 1-800-LATTICE FLEX10K20

    flex 10k20

    Abstract: FLEX10K20
    Text: SONET Interrupt Controller Introduction Overview SONET Synchronous Optical Network is a standard for transmission of data over optical fiber. The SONET format allows different types of formats to be transmitted over the same fiber optic line. The ispLSI 8840 is used in the port shelf section of the


    Original     		PDF Flex10K20RB240-4 Flex10K20. flex 10k20 FLEX10K20

    flex10k20

    Abstract: flex 10k20 an8034
    Text: SONET Interrupt Controller Introduction Overview SONET Synchronous Optical Network is a standard for transmission of data over optical fiber. The SONET format allows different types of formats to be transmitted over the same fiber optic line. The ispLSI 8840 is used in the port shelf section of the


    Original     		PDF Flex10K20RB240-4 Flex10K20. flex10k20 flex 10k20 an8034

    an8034

    Abstract: Lattice bidirectional
    Text: SONET Interrupt Controller Introduction Overview SONET Synchronous Optical Network is a standard for transmission of data over optical fiber. The SONET format allows different types of formats to be transmitted over the same fiber optic line. The ispMACH 51024VG is used in the port shelf section


    Original     		PDF 51024VG 1-800-LATTICE an8034 Lattice bidirectional

    design of scrambler and descrambler

    Abstract: XAPP651 vhdl code scrambler vhdl code for clock and data recovery Scrambler vhdl code for phase shift OC192 OC48 XAPP652 127-bit
    Text: Application Note: Virtex and Virtex-II Families R XAPP651 v1.1 November 15, 2002 SONET and OTN Scramblers/Descramblers Author: Nick Sawyer Summary This application note examines the design of scramblers for use with Synchronous Optical NETworks (SONET) and Optical Transport Unit (OTN) designs using the Virtex series of


    Original     		PDF XAPP651 xapp651 design of scrambler and descrambler vhdl code scrambler vhdl code for clock and data recovery Scrambler vhdl code for phase shift OC192 OC48 XAPP652 127-bit

    OC-768

    Abstract: 84856M209 of optical fpgas xilinx virtex-II
    Text: SPIRENT COMMUNICATIONS SELECTS XILINX VIRTEX-II PLATFORM FPGAS . Page 1 of 2 FOR IMMEDIATE RELEASE SPIRENT COMMUNICATIONS SELECTS XILINX VIRTEX -II PLATFORM FPGAS FOR 40G OPTICAL TRANSPORT ANALYZER Most powerful Xilinx FPGAs provide competitive advantage


    Original     		PDF OC-768 84856M209) \esp\ccstories\spirent0283 84856M209 of optical fpgas xilinx virtex-II

    vhdl code for 8 bit barrel shifter

    Abstract: verilog code for barrel shifter vhdl code for 16 prbs generator vhdl code for loop filter of digital PLL ML523 vhdl code for 4 bit barrel shifter 8 bit barrel shifter vhdl code vhdl code for phase frequency detector verilog code of parallel prbs pattern generator prbs pattern generator using vhdl
    Text: Application Note: Virtex-5 FPGAs Dynamically Programmable DRU for High-Speed Serial I/O XAPP875 v1.1 January 13, 2010 Summary Author: Paolo Novellini and Giovanni Guasti Multi-service optical networks today require the availability of transceivers that can operate


    Original     		PDF XAPP875 vhdl code for 8 bit barrel shifter verilog code for barrel shifter vhdl code for 16 prbs generator vhdl code for loop filter of digital PLL ML523 vhdl code for 4 bit barrel shifter 8 bit barrel shifter vhdl code vhdl code for phase frequency detector verilog code of parallel prbs pattern generator prbs pattern generator using vhdl

    verilog code for barrel shifter

    Abstract: vhdl code for 8 bit barrel shifter vhdl code for 4 bit barrel shifter vhdl code Pseudorandom Streams Generator XAPP875 vhdl code for 16 prbs generator vhdl code for loop filter of digital PLL prbs generator using vhdl prbs pattern generator using vhdl vhdl code for clock and data recovery
    Text: Application Note: Virtex-5 FPGAs Dynamically Programmable DRU for High-Speed Serial I/O XAPP875 v1.0 March 9, 2009 Summary Author: Paolo Novellini and Giovanni Guasti Multi-service optical networks today require the availability of transceivers that can operate


    Original     		PDF XAPP875 verilog code for barrel shifter vhdl code for 8 bit barrel shifter vhdl code for 4 bit barrel shifter vhdl code Pseudorandom Streams Generator XAPP875 vhdl code for 16 prbs generator vhdl code for loop filter of digital PLL prbs generator using vhdl prbs pattern generator using vhdl vhdl code for clock and data recovery

    DPS module

    Abstract: No abstract text available
    Text: Applications Networking Virtex-II Platform FPGAs Support System Packet Interface Standards for Optical Networks The production release of SPI-4 Phase 2 cores to Xilinx communication customers worldwide, is a critical technology boost for multi-service, packet, and cell-based networking equipment.


    Original     		PDF OC-192 10-channel DPS module

    tcam

    Abstract: ternary content addressable memory 100GbE Altera Stratix V datasheets of optical fpgas 100g phy interlaken network processor receiver ber fec 100G 40GBASE-R 10Gbase-kr transmitter
    Text: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs WP-01128-1.1 White Paper As various standard bodies finalize their 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want


    Original     		PDF 100-GbE 28-nm WP-01128-1 40-GbE/100-GbE tcam ternary content addressable memory 100GbE Altera Stratix V datasheets of optical fpgas 100g phy interlaken network processor receiver ber fec 100G 40GBASE-R 10Gbase-kr transmitter

    night-vision digital goggle

    Abstract: Cyclone camera link Altera Cyclone IV FP-5500 altera Date Code Formats Cyclone 2 Fairchild Imaging Altera Digital Camera Development Platform focal plane array defective pixel correction test block diagram of Video graphic array
    Text: Enabling Low-Power EO/IR System Development with FPGAs and Image- and Enabling Low-Power EO/IR System Development with FPGAs and Image- and Sensor-Processing IP WP-01129-1.0 White Paper Before embarking on the development of a next-generation electro-optical and infrared EO/IR


    Original     		PDF WP-01129-1 FP-5500 night-vision digital goggle Cyclone camera link Altera Cyclone IV altera Date Code Formats Cyclone 2 Fairchild Imaging Altera Digital Camera Development Platform focal plane array defective pixel correction test block diagram of Video graphic array

    DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER

    Abstract: verilog code for barrel shifter kcpsm3 picoblaze kcpsm3 verilog code for 64 bit barrel shifter ML525 barrel shifter using verilog IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER SFI-5 DS202
    Text: Application Note: Virtex-5 FPGAs R SERDES Framer Interface Level 5 Author: Ralf Krueger XAPP871 v1.0 February 28, 2008 Summary This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) in a Virtex-5 XC5VLX330T FPGA. SFI-5 is a standard defined by the Optical


    Original     		PDF XAPP871 XC5VLX330T DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER verilog code for barrel shifter kcpsm3 picoblaze kcpsm3 verilog code for 64 bit barrel shifter ML525 barrel shifter using verilog IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER SFI-5 DS202

    free transistor equivalent book 2sc

    Abstract: uPA1556AH The Japanese Transistor Manual 1981 samsung UHF/VHF TV Tuner MOSFET cross-reference 2sk PD431000A-X upper arm digital sphygmomanometer circuit diagram PD72001 uPC1237 uPC 2002
    Text: SEMICONDUCTORS SELECTION GUIDE Microcomputer 1 IC Memory 2 Semi-Custom IC 3 Particular Purpose 4 General Purpose Linear IC 5 Transistor/Diode/Thyristor 6 RF and Microwave Devices 7 Optical Device 8 Index 9 April 1999 The export of these products from Japan is regulated by the Japanese government. The export of some or all of


    Original     		PDF X10679EJHV0SG00 free transistor equivalent book 2sc uPA1556AH The Japanese Transistor Manual 1981 samsung UHF/VHF TV Tuner MOSFET cross-reference 2sk PD431000A-X upper arm digital sphygmomanometer circuit diagram PD72001 uPC1237 uPC 2002

    Untitled

    Abstract: No abstract text available
    Text: Success Story XCITE VIPswitch Partners with Xilinx to Move Beyond ASICs Remotely programmable chips are a perfect fit for new line of Optical Terabit Routers. by Beverly Wilks Director, Marketing Communications, VIPswitch [email protected] offered the best price, reliability, and the


    Original     		PDF

    10G Ethernet PHy

    Abstract: STM-64 infiniband Physical Medium Attachment 0C-48 LVPECL XGC1120
    Text: New RocketPHY Transceiver Family Debuts at 10 Gbps A new family of 10 Gbps serial I/O transceivers dramatically cuts costs in light-speed applications. These transceivers make it possible to create unique optical connectivity designs. by Robert Bielby Senior Director, Strategic Solutions Marketing


    Original     		PDF OC-192 10G Ethernet PHy STM-64 infiniband Physical Medium Attachment 0C-48 LVPECL XGC1120

    rtl8363

    Abstract: rb60 bridge rectifier
    Text: Data Sheet May 2012 MAX24288 EV KIT Evaluates: MAX24288 General Description The MAX24288 EV Kit is an easy-to-use evaluation kit for the MAX24288 IEEE 1588 Packet Timestamper and Clock. On the network side of the MAX24288 an SFP module cage supports either a 1000BASE-X optical


    Original     		PDF MAX24288 MAX24288 1000BASE-X 10/100/1000Mbps RJ-45 rtl8363 rb60 bridge rectifier

    XC6VLX240T

    Abstract: XAPP882 verilog code of prbs pattern generator verilog code for 64 bit barrel shifter verilog code for 16 bit barrel shifter SFI-5 XC6V 4 bit barrel shifter using mux verilog code for barrel shifter DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER
    Text: Application Note: Virtex-6 Family SERDES Framer Interface Level 5 for Virtex-6 Devices Author: Vasu Devunuri XAPP882 v1.1 May 10, 2010 Summary This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical


    Original     		PDF XAPP882 XC6VLX240T XAPP882 verilog code of prbs pattern generator verilog code for 64 bit barrel shifter verilog code for 16 bit barrel shifter SFI-5 XC6V 4 bit barrel shifter using mux verilog code for barrel shifter DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER

    Untitled

    Abstract: No abstract text available
    Text: ML630 Virtex-6 HXT FPGA Optical Transmission Network Evaluation Board User Guide UG828 v1.0 September 28, 2011 The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL


    Original     		PDF ML630 UG828 ML630 om/products/boards-and-kits/EK-V6-ML630-G com/products/boards/ml630/reference

    QSFP

    Abstract: MPLS over optical packet switching OTU1 PDH/SDH stm 4 muxponder ethernet over sdh QSFP 40G transceiver stm 16 muxponder STM-16 Architecture ethernet over pdh
    Text: Optical Transport Networks for 100G Implementation in FPGAs WP-01115-1.1 White Paper Based on announcements from vendors, enterprises and service providers, 100G system deployment is finally gaining real traction in the marketplace. The primary driver for this deployment is the customers’ ceaseless demand for higher bandwidth.


    Original     		PDF WP-01115-1 ieee802 QSFP MPLS over optical packet switching OTU1 PDH/SDH stm 4 muxponder ethernet over sdh QSFP 40G transceiver stm 16 muxponder STM-16 Architecture ethernet over pdh

    interlaken

    Abstract: Altera Cyclone IV sfp design kit of optical fpgas 100G Development Kit
    Text: Stratix IV GT FPGA design resources for 100G applications Altera offers two design resources to help you evaluate Stratix IV GT FPGAs: a signal integrity development kit and a 100G demo board. Ideal for high-bandwidth 40G and 100G applications, Stratix IV GT FPGAs are the market’s lowest power high-density, high-performance FPGAs with


    Original     		PDF 10-Gbps SS-01064-1 interlaken Altera Cyclone IV sfp design kit of optical fpgas 100G Development Kit

    Altera Stratix V

    Abstract: 10G EPON EPON based VOIP by Cisco 10g EPON ONU EPON ONU 10g EPON olt Optical-Splitter MDU FTTH design 10G-EPON 10G-EPON ONU
    Text: Implementing Next-Generation Passive Optical Network Designs with FPGAs WP-01143-1.1 White Paper Passive optical network PON technology is emerging as the key access technology, as it has a scalable and cost-effective architecture to satisfy the ever-growing


    Original     		PDF WP-01143-1 Altera Stratix V 10G EPON EPON based VOIP by Cisco 10g EPON ONU EPON ONU 10g EPON olt Optical-Splitter MDU FTTH design 10G-EPON 10G-EPON ONU

    ROADM

    Abstract: Altera Stratix V muxponder 2.5G DWDm OC192
    Text: White Paper Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs The rapid growth in bandwidth required to support video and broadband wireless is straining communication networks. The current 10-Gbit OTN infrastructure is facing bandwidth exhaustion as the channels approach their


    Original     		PDF 100-Gbit 28-nm 10-Gbit 10-Gbit-based ROADM Altera Stratix V muxponder 2.5G DWDm OC192

    pcie gen3

    Abstract: 10GBASE-KR interlaken optical 400G CPRI multi rate 400G M20K 28Gbps 100g phy Stratix V
    Text: Stratix V FPGAs: Built for Bandwidth Meeting Bandwidth Demands Mobile video, audio/video streaming, cloud computing—these are just a few of the many applications driving up bandwidth demands for the underlying communications infrastructure. To be successful, your next-generation products


    Original     		PDF 28-nm GB-01009-3 pcie gen3 10GBASE-KR interlaken optical 400G CPRI multi rate 400G M20K 28Gbps 100g phy Stratix V

    SFP LVDS

    Abstract: SFP LVDS altera SFP altera sgmii sgmii mode sfp SFP sgmii altera circuit diagram of PPM transmitter and receiver 8B10B fpga ethernet sgmii AN-518-1
    Text: SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Application Note 518 May 2008, version 1.0 Introduction Stratix III device family are one of the most architecturally advanced, high performance, and low power FPGAs available in the market place.


    Original     		PDF