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    O182 Price and Stock

    TE Connectivity NB-PTCO-182

    SENSOR RTD 2SIP
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    DigiKey NB-PTCO-182 Box 1,376 1
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    Mouser Electronics NB-PTCO-182
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    Interstate Connecting Components NB-PTCO-182
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    Richardson RFPD NB-PTCO-182 5,000
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    Avnet Abacus NB-PTCO-182 22 Weeks 5,000
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    Master Electronics NB-PTCO-182
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    Sager NB-PTCO-182 500
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    Vishay Beyschlag WYO182MCMBF0KR

    CAP CER 1800PF 440VAC Y5U RADIAL
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    DigiKey WYO182MCMBF0KR Bulk 16,000
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    Remington Industries CS26MILWSTRBRO-18-25

    C&S #26 MIL-W BRO 18" X 25PCS
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    DigiKey CS26MILWSTRBRO-18-25 Bulk 1
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    Remington Industries CS28MILWSTRVIO-18-250

    C&S #28 MIL-W VIO 18" X 250PCS
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    DigiKey CS28MILWSTRVIO-18-250 Bulk 1
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    Remington Industries CS24UL1061STRBRO-18-25

    C&S #24 UL1061 BRO 18" X 25PCS
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    DigiKey CS24UL1061STRBRO-18-25 Bulk 1
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    O182 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    70V3569

    Abstract: A12L A13L IDT70V3569 IDT70V3569S
    Text: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3569S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access


    Original     		PDF IDT70V3569S 133MHz 133MHz wri12/99: 133MHz, 70V3569 A12L A13L IDT70V3569 IDT70V3569S

    CY37384

    Abstract: CY37384V
    Text: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes


    Original     		PDF CY37384 384-Macrocell CY37384 CY37384V

    d4184

    Abstract: transistor N14 193 atmel application note AT6002 AT6003 AT6005 AT6010
    Text: Features • High-performance • • • • • • • • • – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Thousands of Registers Cache Logic Design


    Original     		PDF 0264F 10/99/xM d4184 transistor N14 193 atmel application note AT6002 AT6003 AT6005 AT6010

    5d3 diode

    Abstract: 6B15 7b12 MACH Programmer transistor 7B12 2D15 PAL 007 A power generator control circuit schematic 1C12 5D10
    Text: MACH 5 CPLD Family I MAC ncludes H Adv anc 5A Fam e In form ily atio n Fifth Generation MACH Architecture FEATURES ◆ High logic densities and I/Os for increased logic integration ◆ ◆ ◆ ◆ ◆ ◆ ◆ — 128 to 512 macrocell densities — 68 to 256 I/Os


    Original     		PDF switLV-256/160 M5A3-256/160 M5A3-192/120 M5LV-256/68 M5A3-256/68 M5LV-512/256-7AC-10AI. 5d3 diode 6B15 7b12 MACH Programmer transistor 7B12 2D15 PAL 007 A power generator control circuit schematic 1C12 5D10

    tdc 310

    Abstract: ba6l BA6R 10 35L U1
    Text: HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip


    Original     		PDF 200MHz 166MHz 133MHz) 14Gbps SMEN-01-04 BF-208 tdc 310 ba6l BA6R 10 35L U1

    ic 4040

    Abstract: 4040 cmos ci 4040 cmos 4040 stv 4325 O129-O135 PD16707 4040
    Text: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社


    Original     		PDF PD16707 PD16707 VDD2-VEE40 PD16707P PD16707N-xxx S16411JJ1V0DS00 200/index PD16707N-xxxTCP SUMIZAC1003 S16411JJ1V0DS ic 4040 4040 cmos ci 4040 cmos 4040 stv 4325 O129-O135 4040

    ba6l

    Abstract: No abstract text available
    Text: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks – 2 megabits of memory on chip


    Original     		PDF 200MHz 166MHz 133MHz) 14Gbps SMEN-01-05 SMEN-01-04 ba6l

    IDT70T659

    Abstract: No abstract text available
    Text: HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features ◆ ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port


    Original     		PDF 256/128K 100mV) 150mV 256-ball 208-pin 208-ball IDT70T659

    10 35L U4

    Abstract: 70V7589 IDT70V7589 IDT70V7589S BA5L
    Text: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V7589S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks


    Original     		PDF IDT70V7589S 166MHz 133MHz) 12Gbps SMEN-01-05 SMEN-01-04 10 35L U4 70V7589 IDT70V7589 IDT70V7589S BA5L

    Untitled

    Abstract: No abstract text available
    Text: 1 MACH 5 FAMILY MACH 5 Family Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ Publication# 20446 Amendment/0 Rev: D Issue Date: August 1997 MACH 5 Family ◆ Fifth generation MACH architecture — 100% routable


    Original     		PDF 16-038-BGD352-1 DT106

    MC189

    Abstract: 9300 4b10 2D15 marking 1A15 HP 3D6 1b61a0 MACH5-320 ae 4b15
    Text: MACH 5 FAMILY 1 FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-320/MACH5LV-320 MACH5-320/120-7/10/12/15 MACH5-320/192-7/10/12/15 MACH5LV-320/184-7/10/12/15 MACH5-320/160-7/10/12/15 MACH5LV-320/120-7/10/12/15 MACH5LV-320/192-7/10/12/15 MACH5-320/184-7/10/12/15


    Original     		PDF MACH5-320/MACH5LV-320 MACH5-320/120-7/10/12/15 MACH5-320/192-7/10/12/15 MACH5LV-320/184-7/10/12/15 MACH5-320/160-7/10/12/15 MACH5LV-320/120-7/10/12/15 MACH5LV-320/192-7/10/12/15 MACH5-320/184-7/10/12/15 MACH5LV-320/160-7/10/12/15 16-038-BGD256-1 MC189 9300 4b10 2D15 marking 1A15 HP 3D6 1b61a0 MACH5-320 ae 4b15

    CY37512

    Abstract: CY37512V
    Text: Back PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes


    Original     		PDF CY37512V 512-Macrocell CY37512 CY37512V

    CY37384

    Abstract: CY37384V cpld internal
    Text: Back PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Features — tPD = 15 ns — tS = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • •


    Original     		PDF CY37384V 384-Macrocell CY37384 CY37384V cpld internal

    4D-13

    Abstract: HP 3D6 making 5A6 3d13 3D-14 5B7 Marking i 384
    Text: MACH 5 FAMILY X FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-384/MACH5LV-384 MACH5-384/120-7/10/12/15 MACH5-384/192-7/10/12/15 MACH5LV-384/184-7/10/12/15 MACH5-384/160-7/10/12/15 MACH5LV-384/120-7/10/12/15 MACH5LV-384/192-7/10/12/15 MACH5-384/184-7/10/12/15


    Original     		PDF MACH5-384/MACH5LV-384 MACH5-384/120-7/10/12/15 MACH5-384/192-7/10/12/15 MACH5LV-384/184-7/10/12/15 MACH5-384/160-7/10/12/15 MACH5LV-384/120-7/10/12/15 MACH5LV-384/192-7/10/12/15 MACH5-384/184-7/10/12/15 MACH5LV-384/160-7/10/12/15 16-038-BGD256-1 4D-13 HP 3D6 making 5A6 3d13 3D-14 5B7 Marking i 384

    70V7519

    Abstract: IDT70V7519 IDT70V7519S ba6l
    Text: Š HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip


    Original     		PDF 200MHz 166MHz 133MHz) 14Gbps BC-256 70V7519 IDT70V7519 IDT70V7519S ba6l

    A17R-A0R

    Abstract: A17L-A0L 7144
    Text: HIGH-SPEED 1.8V 256/128K x 36 IDT70P3519/99 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V/2.5V/1.8V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location Low Power High-speed data access


    Original     		PDF 256/128K IDT70P3519/99 200MHz 166MHz) 14Gbps 200MHz 5T2010 5T9010 A17R-A0R A17L-A0L 7144

    2ED020I06-FI

    Abstract: infineon igbt die 650V
    Text: Datasheet, April 2010 2ED020I06-FI Dual IGBT Driver IC April 2010 Power Managment & Drives N e v e r s t o p t h i n k i n g . 2ED020I06-FI Revision History: 2010-04-20 Datasheet Previous Version: Page Subjects major changes since last revision For questions on technology, delivery and prices, please contact the Infineon offices in Germany or the Infineon companies


    Original     		PDF 2ED020I06-FI D-85579 2ED020I06-FI infineon igbt die 650V

    O23R

    Abstract: o32l 70V3579 A12L A14L IDT70V3579 IDT70V3579S optl p2 3.5mm
    Text: Š HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V3579S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access


    Original     		PDF IDT70V3579S 133MHz 133MHz O23R o32l 70V3579 A12L A14L IDT70V3579 IDT70V3579S optl p2 3.5mm

    CABGA

    Abstract: fpga JTAG Programmer Schematics AT17 AT40K AT94K AT94S AT94S05AL AT94S10AL AT94S40AL C16107
    Text: Features • Multichip Module Containing Field Programmable System Level Integrated Circuit • • • • • • • • • • • • • • • • • FPSLIC and Secure Configuration EEPROM Memory 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System


    Original     		PDF AT40K 2314D CABGA fpga JTAG Programmer Schematics AT17 AT94K AT94S AT94S05AL AT94S10AL AT94S40AL C16107

    IDT70T3589

    Abstract: IDT70T3599 70T359 70T3589
    Text: HIGH-SPEED 2.5V 256/128/64K x 36 IDT70T3519/99/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access


    Original     		PDF 256/128/64K IDT70T3519/99/89S 200MHz 166MHz 133MHz) 14Gbps IDT70T3589 IDT70T3599 70T359 70T3589

    70T3589

    Abstract: No abstract text available
    Text: HIGH-SPEED 2.5V 256/128/64K x 36 IDT70T3519/99/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access


    Original     		PDF 256/128/64K IDT70T3519/99/89S 200MHz 166MHz 133MHz) 14Gbps 70T3589

    Untitled

    Abstract: No abstract text available
    Text: Š Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT70T651/9S HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port


    Original     		PDF IDT70T651/9S 256/128K 100mV) 150mV 256-ball 208-pin 208-ball

    clcc land pattern

    Abstract: CY37512VP208-66UMB CY37032VP44-100AI CY37064P44-154YMB CY37256P160-125UMB TO-220AB/clcc land pattern
    Text: CYPRESS PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs General Description Features • In-System Reprogram mable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes


    OCR Scan     		PDF Ultra37000TM Ultra37000 22V10 clcc land pattern CY37512VP208-66UMB CY37032VP44-100AI CY37064P44-154YMB CY37256P160-125UMB TO-220AB/clcc land pattern

    CL 6017

    Abstract: No abstract text available
    Text: o R EL EA S ED FOR P U B L I C A T I O N E ' CONSENTITA LA DI VUL GAZ IO NE ALL R IGH TS R ES E R V ED . INCORPORATED. TUTTI I D I R I T T I SONO R I S E R V A T I T H I S DRAWING IS UN P UB LI SH E D. QUESTO DISE GNO NON DEVE E S S E R E DIVULGATO 0 RI PRODOTTO


    OCR Scan     		PDF ET00-0283-96 ET00-0465-97 O182-99 ETOO-O149-00 09MAY94 CL 6017