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    NIBBLE MODE Search Results

    NIBBLE MODE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    FO-9LPBMTRJ00-001 Amphenol Cables on Demand Amphenol FO-9LPBMTRJ00-001 MT-RJ Connector Loopback Cable: Single-Mode 9/125 Fiber Optic Port Testing .1m Datasheet
    SF-XP85B102DX-000 Amphenol Cables on Demand Amphenol SF-XP85B102DX-000 SFP28 25GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (Duplex LC Connector) by Amphenol XGIGA [XP85B102DX] Datasheet
    SF-QXP85B402D-000 Amphenol Cables on Demand Amphenol SF-QXP85B402D-000 QSFP28 100GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (MTP/MPO Connector) by Amphenol XGIGA [QXP85B402D] Datasheet
    FO-DLSCDLLC00-002 Amphenol Cables on Demand Amphenol FO-DLSCDLLC00-002 SC-LC Duplex Single-Mode 9/125 Fiber Optic Patch Cable (OFNR Riser) - 2 x SC Male to 2 x LC Male 2m Datasheet
    FO-LSDUALSCSM-003 Amphenol Cables on Demand Amphenol FO-LSDUALSCSM-003 SC-SC Duplex Single-Mode 9/125 Fiber Optic Patch Cable (OFN-LS Low Smoke) - 2 x SC Male to 2 x SC Male 3m Datasheet

    NIBBLE MODE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    S3031B

    Abstract: No abstract text available
    Text: Part Number S3031B Revision 1.0 - January 29, 2000 S3031B APPLICATION NOTE Nibble Mode Timing Characteristics S3031B Transceiver Nibble Mode Setup and Hold The S3031B has the following timing characteristics on the Nibble input and output pins: Table 1. Receiver Timing Characteristics


    Original     		PDF S3031B S3031B

    4.096MHz

    Abstract: No abstract text available
    Text: Application Note MSAN-175 Performing Nibble and Dibit Switching with the MT90820 LDX ISSUE 1 April 1998 Contents 1.0 Introduction 1.0 Introduction 2.0 Switching Configurations 2.1 Dibit Switching 2.2 Nibble Switching Dibit switching (2 bits per channel) is essential to the


    Original     		PDF MSAN-175 MT90820 16Kb/s 4.096MHz

    Untitled

    Abstract: No abstract text available
    Text: June 1990 Edition 2.0 — FUJITSU DATA SHEET MB814101-80/-10/-12 CMOS 4,194,304 BIT NIBBLE MODE DYNAMIC RAM CMOS 4,194,304 x 1 Bit Nibble Mode Dynamic RAM The Fujitsu MB814101 is a fully decoded CMOS dynamic RAM DRAM that contains a total of 4,194,304 memory calls in a x 1 configuration. The MB814101 features a nibble


    OCR Scan     		PDF MB814101-80/-10/-12 MB814101 26-LEAD MB814101-80 MB814101-10 MB814101-12

    Untitled

    Abstract: No abstract text available
    Text: June 1990 Editar 2.0 FUJITSU D A TA S H E E T — MB814101-80/-10/-12 CMOS 4,194,304 BIT NIBBLE MODE DYNAMIC RAM CMOS 4,194,304 x 1 Bit Nibble Mode Dynamic RAM The Fujitsu MB814101 is afully decoded CMOS dynamic RAM DRAM) that contains a total of 4,194,304 memory celte in ax 1 configuration. The MB814101 features a nibble


    OCR Scan     		PDF MB814101-80/-10/-12 MB814101 26-lead C26064S-1C MB814101-80 MB814101-10 MB814101-12

    Untitled

    Abstract: No abstract text available
    Text: September 1993 Edition 3.1 FUJITSU DATA SHEET MB8116101-60/-70/-80 CM O S 16M x 1 B IT NIBBLE M O D E DYNAMIC RAM CMOS 16,777,216 x 1 BIT Nibble Mode Dynamic RAM The Fujitsu MB8116101 is a fully decoded CMOS Dynamic RAM DRAM that contains a total of 16,777,216 memory cells in a x1 configuration. The MB8116101 features a "nibble" mode of


    OCR Scan     		PDF MB8116101-60/-70/-80 MB8116101 096-bits V32002S-5C

    MB814101-80U-10U-12L

    Abstract: No abstract text available
    Text: November 1990 Edition 1.0 FUJITSU DATA SHEET MB814101-80U-10U-12L CMOS 4M x 1 BIT NIBBLE MODE LOW POWER DYNAMIC RAM CM O S 4M x 1 Bit Nibble Mode Low Power Dynamic RAM The Fujitsu MB814101 isafullydecodedCMOSdynam ic R A M DRAM that containsa total of 4,194,304 memory cells in ax 1 configuration. The MB814101 features a nibble


    OCR Scan     		PDF MB814101-80U-10U-12L MB814101 FPT-26P-M MB814101-80U-10U-12L

    Static RAM fujitsu

    Abstract: ZIP-20P-M02
    Text: FUJITSU November 1990 Edition 1.0 M B814101-80U-10U-12L CMOS 4M x 1 B IT NIBBLE M O DE LO W POW ER DYNAMIC RAM CMOS 4M x 1 Bit Nibble Mode Low Power Dynamic RAM The Fujitsu MB814101 is afu lly decoded CM OS dynam ic RAM DRAM that contains a total of 4,194,304 memory cells in a x 1 configuration. TheM B814101 features a nibble


    OCR Scan     		PDF MB814101-80U-10U- MB814101 FPT-26P-M01 FPT-26P-M02 Static RAM fujitsu ZIP-20P-M02

    Untitled

    Abstract: No abstract text available
    Text: November 1992 Edition 1.0 FUJITSU DATA SHEET M B 8 1 1 7 1 0 1 -60/-70/-80 CMOS 16M x 1 BIT NIBBLE MODE DYNAMIC RAM CMOS 16,777,216 x 1 BIT Nibble Mode Dynamic RAM The Fujitsu MB8117101 is a fully decoded CMOS Dynamic RAM DRAM that contains a total of 16,777,216 memory cells in a x1 configuration. The MB8117101 features a "nibble” mode of


    OCR Scan     		PDF MB8117101 096-bits KV0008-92YK1

    krania

    Abstract: 9j16 MB814101-10 MB814101-80
    Text: FuflTSU June 1990 Edition 2.0 M B 8 1 4 1 0 1 -80/-10/-12 CMOS 4,194,304 B IT NIBBLE M O D E DYNAMIC RAM CMOS 4,194,304 x 1 Bit Nibble Mode Dynamic RAM The Fujitsu MB814101 is a f ully decoded C M O S dynamic RAM DRAM that contains a total o f4,194,304 memory ceils in a x 1 configuration. The MB814101 features a nibble


    OCR Scan     		PDF MB814101-80/-10/-12 MB814101 C2B053S-1C MB814101-80 20-LEAD krania 9j16 MB814101-10 MB814101-80

    AM90C255-10

    Abstract: AM90C255-12 uras 14
    Text: Am90C255 256K x 1 CMOS Nibble Mode Dynamic RAM PRELIMINARY SSZ006UIV DISTINCTIVE CHARACTERISTICS • • • • High density 256K x 1 Low-power dissipation — 358 mW active High-speed operation — 80-ns access, 130-ns cycle times High-speed Nibble Mode


    OCR Scan     		PDF Am90C255 80-ns 130-ns 15-ns 35-ns appl09712 WF009731 WF009742 AM90C255-10 AM90C255-12 uras 14

    e33i

    Abstract: IC1001
    Text: November 1990 Edition 2.0 FUJITSU DATA SHEET MB81C1001A-70L/-80L/-WL CMOS 1,048,576 BIT NIBBLE MODE DYNAMIC RAM CMOS 1M x 1 Bit Nibble Mode DRAM The Fujitsu M B81C1001A is a CMOS, fully decoded dynamic RAM organized as 1,048,576 words x 1 bit. The MB81C1001A has been designed lor mainframe


    OCR Scan     		PDF MB81C1001A-70L/-80L/-WL B81C1001A MB81C1001A 24-LEAD FPT-24P-M04) F24020S-2C MB81C1001A-70L MB81C1001A-80L MB81C1001A-10L e33i IC1001

    Untitled

    Abstract: No abstract text available
    Text: J K M 4 1 2 5 7 /K M 4 1 2 5 7 A SA M SU N G Semiconductor KM41257/KM41257A 262,144 x 1 Bit Dynamic RAM with Nibble Mode JULY 1987 FEATURES • Performance range: The KM41257/A features nibble mode which allows


    OCR Scan     		PDF KM41257/KM41257A KM41257/A

    Untitled

    Abstract: No abstract text available
    Text: Am90C255 256K x 1 CMOS Nibble Mode Dynamic RAM Am90C255 PRELIMINARY DISTINCTIVE CHARACTERISTICS • • • • High density 256K x 1 Low-power dissipation — 358 mW active High-speed operation — 80-ns access, 130-ns cycle times High-speed Nibble Mode - 15-ns access, 35-ns cycle times


    OCR Scan     		PDF Am90C255 80-ns 130-ns 15-ns 35-ns 90C255 WF009742 WF009752

    MB81C1001-12

    Abstract: MB81C1001-10 81C100 81c1001 MB81C1001 MB81C1001-70 MB81C1001-80 EI96
    Text: February 1990 Edition 3.0 FUJITSU MB81C100 1 -70/-80/-10/-12 CMOS 1,048,576 BIT NIBBLE MODE DYNAMIC RAM CMOS 1M x 1 Bit Nibble Mode DRAM The Fujitsu MB81C1001 is a CMOS, fully decoded dynamic RAM organized as 1,048,576 words x 1 bit. The MB81C1001 has been designed for mainframe


    OCR Scan     		PDF MB81C1001-70/-80/-W/-12 MB81C1001 26-lead ei969 C260HS-1C MB81C1001-70 MB81C1001-80 MB81C1001-12 MB81C1001-10 81C100 81c1001 EI96

    RD4A

    Abstract: No abstract text available
    Text: XBERT Device Bit Error Rate Generator Receiver TXC-06125 DATA SHEET Preliminary FEATURES = — — — - = • Serial, nibble, or byte wide interface capability • Transmit and receive clock rate: 100 Hz to 52.00 MHz serial, byte, nibble I/O (All telecom rates


    OCR Scan     		PDF TXC-06125 T0041S2 RD4A

    Untitled

    Abstract: No abstract text available
    Text: June 1991 Edition 4.0 FUJITSU DATA SHEET M B 8 1 C 1 0 0 1 A - 6 0 /- 7 0 /- 8 0 / - 1 0 CMOS 1M x 1 BIT NIBBLE MODE DYNAMIC RAM CMOS 1,048,576 X 1 Bit Nibble Mode DRAM The Fujitsu MB81C1001AisaCMC>S, fully decoded dynamic RAM organized as 1,048,576 words


    OCR Scan     		PDF MB81C1001AisaCMC MB81C1001A F24020S-3C MB81C1001A-60 MB81C1001A-70 MB81C1001A-80 MB81C1001A-10 24-LEAD FPT-24P-M05)

    916J

    Abstract: No abstract text available
    Text: June 1991 Edition 3.0 FUJITSU DATA SHEET M B 8 1 C 1 0 0 1 A - 70L/-80L/-10L CMOS 1M x 1 BIT NIBBLE MODE LOW POWER DRAM CMOS 1,048,576 X 1 Bit Nibble Mode Low Power DRAM The Fujitsu MB81C1001A is a CMOS, fully decoded dynamic RAM organized as 1,048,576 words


    OCR Scan     		PDF 70L/-80L/-10L MB81C1001A JV0056-916J3 916J

    Untitled

    Abstract: No abstract text available
    Text: I KM41C4001A ^ CM OS DRAM 4 M X 1 Bit CMOS Dynamic RAM with Nibble Mode FEATURES GENERAL DESCRIPTION Performance range: tR A C tC A C tRC 70ns 20ns 130ns KM 41C4001 A- 8 80ns 20ns 1 50ns K M 41C 4001A -10 100ns 25ns 1 80ns KM 41C4001 A- 7 Nibble Mode operation


    OCR Scan     		PDF KM41C4001A 41Codify-write 18-LEAD 20-LEAD

    Untitled

    Abstract: No abstract text available
    Text: Am90C255 256K x 1 CMOS Nibble Mode Dynamic RAM PRELIMINARY SSZ006WV DISTINCTIVE CHARACTERISTICS • • • High density 256K x 1 Low-power dissipation — 358 mW active High-speed operation — 80-ns access, 130-ns cycle times • High-speed Nibble Mode - 15-ns access, 35-ns cycle times


    OCR Scan     		PDF Am90C255 SSZ006WV 80-ns 130-ns 15-ns 35-ns WF009712 WF009742

    Untitled

    Abstract: No abstract text available
    Text: February 1990 Edition 3.0 FUJITSU DATA SHEET : MB81C1001-70/-80/-10/-12 CMOS 1,048,576 BIT NIBBLE MODE DYNAMIC RAM CMOS 1M x 1 Bit Nibble Mode DRAM The Fujitsu MB81C1001 is a CMOS, fully decoded dynamic RAM organized as 1,048,576 words x 1 bit. The MB81C1001 has been designed for mainframe


    OCR Scan     		PDF MB81C1001-70/-80/-10/-12 MB81C1001 LCC-26P-M04) C260MS-1C MB81C1001-70 MB81C1001-80 MB81C1001-10

    Untitled

    Abstract: No abstract text available
    Text: June 1991 Edition 4.0 FUJITSU DATA SHEET MB81C1001A-60/-70/-80/-10 CMOS 1 Mx 1 BIT NIBBLE MODE DYNAMIC RAM CMOS 1,048,576 X 1 Bit Nibble Mode DRAM The Fujitsu MB81C1001A is a CMOS, fully decoded dynamic RAM organized as 1,048,576 words x 1 bit. The MB81C1001A has been designed for mainframe memories, buffer memories, and


    OCR Scan     		PDF MB81C1001A-60/-70/-80/-10 MB81C1001A and67 MB81C1001A-60 MB81C1001A-70 MB81C1001A-80 MB81C1001A-10 24-LEAD

    Untitled

    Abstract: No abstract text available
    Text: F£B u FUJITSU October 1992 Edition 1.1 DATA SHEET M B S 8 1 3 2 1 0 1 - 6 0 /- 7 0 / - 8 0 CMOS 32M x 1 BIT NIBBLE MODE DYNAMIC RAM CMOS 33,554,432 x 1 BIT Nibble Mode Dynamic RAM Fujitsu MBS8132101 is a fully decoded CMOS Dynamic RAM DRAM that contains a total of


    OCR Scan     		PDF MBS8132101 096-bits

    flip-flop 948

    Abstract: 5252 f 1101 SN74AS8840 CNTR11-CNTR8 Zeus Component AS8832
    Text: SN74AS8840. Digital Crossbar Switch • High-speed programmable switch for parallel processing applications • Dynam ically reconfigurable for fault-tolerant routing • 64 bidirectional data I/O s in 16 nibble four-bit groups • D ata I/O selection programmable by nibble


    OCR Scan     		PDF SN74AS8840. SN74AS8840 can14) flip-flop 948 5252 f 1101 CNTR11-CNTR8 Zeus Component AS8832

    nibble mode

    Abstract: No abstract text available
    Text: Electronic Designs Inc. EDH44256N-10/12/15 256K x 4 DRAM NIBBLE MODE The EDH44256N has nibble mode capacity, yielding access to 16 bits at one time. The EDH44256N is intended for use in any application where large quantities of memory are required and/or board space is of prime concern. General


    OCR Scan     		PDF EDH44256N-10/12/15 EDH44256N nibble mode