corrosion
Abstract: Mecatraction JUPITER e series connector MS JUPITER e series connector E44-E43 CM-501-MS MSH Connectors MSH 14 Connectors burndy GROUNDING CONNECTORS RG302
Text: MSH/MPH series Connectors Connectors for for navy navy applications applications and and heavy heavy duty duty industries industries MSH/MPH series Connectors and interconnect systems for harsh environments The company designs, manufactures and markets high performance interconnect solutions for severe environments
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2006E
corrosion
Mecatraction
JUPITER e series connector MS
JUPITER e series connector
E44-E43
CM-501-MS
MSH Connectors
MSH 14 Connectors
burndy GROUNDING CONNECTORS
RG302
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TMx390
Abstract: SuperSPARC STP1020 STP1021A MAD19 STP1091 ADDR02 Mbus master 250 slave circuit stp1090 imad-26
Text: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM STP1091 July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC DESCRIPTION The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus system is required.
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STP1091
STP1091
STP1020
STP1021
33x8k
TMx390
SuperSPARC
STP1020
STP1021A
MAD19
ADDR02
Mbus master 250 slave circuit
stp1090
imad-26
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transistor p710
Abstract: 73D34 AD1871 ADSP-TS101S psdsoft express 8.6 ADSP-TS101 AD1854 rd msh murata msh CT1112
Text: ADSP-TS101S EZ-KIT Lite Evaluation System Manual Revision 2.1, April 2006 Part Number 82-000635-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2006 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent
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ADSP-TS101S
transistor p710
73D34
AD1871
psdsoft express 8.6
ADSP-TS101
AD1854
rd msh
murata msh
CT1112
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tms 3899
Abstract: tms 3614 TMS320VC549 CI 7431 delay timer S-PBGA-N144
Text: TMS320VC549 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS078D – SEPTEMBER 1998 – REVISED DECEMBER 1999 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU
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TMS320VC549
SPRS078D
16-Bit
40-Bit
17-Bit
tms 3899
tms 3614
CI 7431 delay timer
S-PBGA-N144
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mc 3842 Circuit diagram
Abstract: xf-72 SMJ320LC549 mp 9141 mc 3842 BDX 163 HD2133
Text: SMJ320LC549 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SGUS032B – OCTOBER 2002 – REVISED MAY 2003 D Processed to MIL-PRF-38535 QML D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus
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SMJ320LC549
SGUS032B
MIL-PRF-38535
16-Bit
40-Bit
17-Bit
mc 3842 Circuit diagram
xf-72
SMJ320LC549
mp 9141
mc 3842
BDX 163
HD2133
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Untitled
Abstract: No abstract text available
Text: SMJ320LC549 FIXED−POINT DIGITAL SIGNAL PROCESSOR SGUS032A - OCTOBER 2002 - REVISED FEBRUARY 2003 D Processed to MIL-PRF-38535 QML D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus
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SMJ320LC549
SGUS032A
MIL-PRF-38535
16-Bit
40-Bit
17-Bit
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Untitled
Abstract: No abstract text available
Text: SMJ320LC549 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SGUS032B – OCTOBER 2002 – REVISED MAY 2003 D Processed to MIL-PRF-38535 QML D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus
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SMJ320LC549
SGUS032B
MIL-PRF-38535
16-Bit
40-Bit
17-Bit
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Untitled
Abstract: No abstract text available
Text: SMJ320LC549 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SGUS032B – OCTOBER 2002 – REVISED MAY 2003 D Processed to MIL-PRF-38535 QML D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus
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SMJ320LC549
SGUS032B
MIL-PRF-38535
16-Bit
40-Bit
17-Bit
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TMDSDSK5416
Abstract: No abstract text available
Text: SMJ320LC549 FIXED−POINT DIGITAL SIGNAL PROCESSOR SGUS032A - OCTOBER 2002 - REVISED FEBRUARY 2003 D Processed to MIL-PRF-38535 QML D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus
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SMJ320LC549
SGUS032A
MIL-PRF-38535
16-Bit
40-Bit
17-Bit
TMDSDSK5416
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TMS320LC549
Abstract: TMS320LC549GGU TMS320VC549
Text: TMS320LC549 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS077B – SEPTEMBER 1998 – REVISED FEBRUARY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU
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TMS320LC549
SPRS077B
16-Bit
40-Bit
17-Bit
TMS320LC549
TMS320LC549GGU
TMS320VC549
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TMS320VC549
Abstract: SPRS078F
Text: TMS320VC549 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU
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TMS320VC549
SPRS078F
16-Bit
40-Bit
17-Bit
TMS320VC549
SPRS078F
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TMS320LC548
Abstract: TMS320LC548GGU BDX0
Text: TMS320LC548 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS123 – FEBRUARY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel Shifter and Two
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TMS320LC548
SPRS123
16-Bit
40-Bit
17-Bit
TMS320LC548
TMS320LC548GGU
BDX0
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Untitled
Abstract: No abstract text available
Text: SMJ320LC549 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SGUS032B – OCTOBER 2002 – REVISED MAY 2003 D Processed to MIL-PRF-38535 QML D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus
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SMJ320LC549
SGUS032B
MIL-PRF-38535
16-Bit
40-Bit
17-Bit
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Untitled
Abstract: No abstract text available
Text: HEADER LINE 1 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS077B – SEPTEMBER 1998 – REVISED FEBRUARY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU
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SPRS077B
16-Bit
40-Bit
17-Bit
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BDX 241
Abstract: bdx 530 TMS320VC549 tms 3899 Non-Pipelined Single-Cycle processor BDR-1
Text: HEADER LINE 1 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS078E – SEPTEMBER 1998 – REVISED JANUARY 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU
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SPRS078E
16-Bit
40-Bit
17-Bit
BDX 241
bdx 530
TMS320VC549
tms 3899
Non-Pipelined Single-Cycle processor
BDR-1
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HAI 7203
Abstract: ACT8847 74ACT8847 SN74 multiplier
Text: TEXAS INSTR LOGIC SSE D 0^1723 GQÖS7G3 7 SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square
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SN74ACT8847
64-Bit
SN74ACT8837
30-ns,
40-ns
50-ns
SN74ACT8847
AGT88X7
HAI 7203
ACT8847
74ACT8847
SN74 multiplier
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SN74ACT8847
Abstract: ACT8847 ti 8847
Text: SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square Root in 14 Cycles
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SN74ACT8847
64-Bit
30-ns,
40-ns
50-ns
ACT88X7
SN74ACT8847
ACT8847
ti 8847
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UT69532
Abstract: signal path designer
Text: Military-Standard Products UT69321IQAGS Address Generator/Sequencer Preliminary Data Sheet UNITED TECHNOLOGIES MICROELECTRONICS CENTER November 1991 FEATURES □ Programmable controller chip for the UT69532 IQMAC pipelined processor □ Generates all control signals necessary to execute any
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UT69321IQAGS
UT69532
signal path designer
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STP1020
Abstract: DATA45 MAD42
Text: Prelimina Sun STP1020 May 19 94 SuperSPARC DÄIA SEET Highly Integrated 32-Bit RISC Microprocessor D e s c r ip t io n The STP1020 is one of the mem bers of the SuperSPARC fam ily of microprocessor products. Like the other members STP1020N and STP1020A , this part is fully SPARC version 8 com pliant and is com
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STP1020
32-Bit
STP1020
STP1020N
STP1020A)
pipe00-out
pipe01
pipe02
pipe03
DATA45
MAD42
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Untitled
Abstract: No abstract text available
Text: Preliminary w STP1020A SPARC Technology Business June 1995 SuperSPARC DATA SHEET Highly Integrated 32-Bit RISC Microprocessor D e s c r i p t io n The STP1020A is a new member of the SuperSPARC family of microprocessor products. Like its pre decessors STP1020N and STP1020 this new part is fully SPARC version 8 compliant and is completely
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STP1020A
32-Bit
STP1020A
STP1020N
STP1020)
Integrated32-Bit
STP1020APGA-60
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Untitled
Abstract: No abstract text available
Text: Prelimina: SIARCTechnology STP1090A Business January Multi-Cache Controller ,TM DATA. SE ET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1090A is a high-perform ance external cache controller for the STP1020A SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used w hen a large secondary cache or an interface
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STP1090A
STP1090A
STP1020A
STP1021
33x8k
STP1020H
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SuperSPARC
Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys
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STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
STP1020HS
STP1091
SuperSPARC
Mbus master 250 slave circuit
tmx390
STP1091-60
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tmx390
Abstract: supersparc PM 438 BL capacitor 471 aj7 tmx390x55 tpvc01
Text: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM S un M ic r o e l e c t r o n ic s July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (Super
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STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
tmx390
supersparc
PM 438 BL
capacitor 471 aj7
tmx390x55
tpvc01
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Untitled
Abstract: No abstract text available
Text: STP1091 S un M ic r o e l e c t r o n ic s J u ly 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-perform ance external cache controller for the STP1020 SuperSPARC and STP1021
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STP1091
STP1091
STP1020
STP1021
33x8k
1091PG
STP1020H
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