8180D18
Abstract: No abstract text available
Text: Advanced Information GS8180D09/18B-333/300/275/250 209-Bump BGA Commercial Temp Industrial Temp ΣRAM 2M x 9, 1M x 18 Separate I/O Sigma DDR SRAM 333 MHz 1.8 V VDD 1.8 V and 1.5 V I/ Features • Double Data Rate Read and Write mode • Observes the Sigma RAM pinout standard
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Original
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PDF
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GS8180D09/18B-333/300/275/250
209-Bump
209-bump,
12rcial
8180D0918
8180D18
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MCL 1 029
Abstract: ECHO schematic diagrams 2000-23 k4 8180S18 8180S36 GS8180S36B-333 Sigma ddr
Text: Advanced Information GS8180S09/18/36B-333/300/275/250 209-Bump BGA Commercial Temp Industrial Temp ΣRAM 2M x 9, 1M x 18, 512K x 36 Separate I/O Sigma SDR SRAM 333 MHz 1.8 V VDD 1.8 V and 1.5 V I/ Features • Observes the Sigma RAM pinout standard • 1.8 V +150/–100 mV core power supply
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Original
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PDF
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GS8180S09/18/36B-333/300/275/250
209-Bump
209-bump,
8180S091836
MCL 1 029
ECHO schematic diagrams
2000-23 k4
8180S18
8180S36
GS8180S36B-333
Sigma ddr
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U8 100E
Abstract: BGA2002 ECHO schematic diagrams GS8170DD36C-300 GS8170DD36C-333
Text: Preliminary GS8170DD18/36C-333/300/250 18Mb Σ1x2Lp Double Data Rate SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Data Rate Read and Write mode • JEDEC-standard SigmaRAM™ pinout and package
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Original
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PDF
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GS8170DD18/36C-333/300/250
209-Bump
209-bump,
209-Pin
GS8170DD18C-333I
GS8170DD18C-300I
GS8170DD18C-250I
U8 100E
BGA2002
ECHO schematic diagrams
GS8170DD36C-300
GS8170DD36C-333
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ECHO schematic diagrams
Abstract: No abstract text available
Text: Preliminary GS8170LW18/36/72C-333/300/250 18Mb Σ1x1 Late Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Late Write mode • Pipeline read operation • JEDEC-standard SigmaRAM™ pinout and package
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Original
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PDF
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GS8170LW18/36/72C-333/300/250
209-Bump
209-bump,
8170LW18
ECHO schematic diagrams
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GS8170D36B-333
Abstract: 8170D18 GS8170D36B-300
Text: Preliminary GS8170D18/36B-333/300/250 209-Bump BGA Commercial Temp Industrial Temp 18Mb Σ1x2Lp DDR SRAM 1M x 18, 512K x 36 250 - 333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Data Rate Read and Write mode • JEDEC standard SigmaRAM pinout and package
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Original
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PDF
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GS8170D18/36B-333/300/250
209-Bump
209-bump,
deviceGS8170D18B-250
209-Pin
GS8170D18B-333I
GS8170D18B-300I
GS8170D18B-250I
GS8170D36B-333
8170D18
GS8170D36B-300
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Untitled
Abstract: No abstract text available
Text: Preliminary GS8170EW18/36/72C-333/300/250 18Mb Σ1x1 Early Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Early Write mode • User-configurable pipeline and flow through operation
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Original
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PDF
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GS8170EW18/36/72C-333/300/250
209-Bump
8170EW18
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ECHO schematic diagrams
Abstract: 8170D18 8170D36 GS8170D36B-300 GS8170D36B-333 Sigma ddr
Text: Advanced Information GS8170D18/36B-333/300/275/250 209-Bump BGA Commercial Temp Industrial Temp ΣRAM 1M x 18, 512K x 36 16Mb DDR SRAM 333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Data Rate Read and Write mode • Observes the Sigma RAM pinout standard
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Original
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PDF
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GS8170D18/36B-333/300/275/250
209-Bump
209-bump,
8170D1836
ECHO schematic diagrams
8170D18
8170D36
GS8170D36B-300
GS8170D36B-333
Sigma ddr
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ECHO schematic diagrams
Abstract: flip chip bga 0,8 mm
Text: Preliminary GS8170DW18/36/72C-333/300/250 18Mb Σ1x1 Double Late Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Late Write mode • JEDEC-standard SigmaRAM™ pinout and package
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Original
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PDF
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GS8170DW18/36/72C-333/300/250
209-Bump
209-bump,
8170DW18
ECHO schematic diagrams
flip chip bga 0,8 mm
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MCL SRA-1
Abstract: No abstract text available
Text: .Y MODEL DOUBLE BALANCED MIXER MD-410 RF, LO 0.5-500 MHz IF D C -500 MHz LO Power +7 dBm Typical Midband Conversion Loss of 5.5 dB MCL Model SRA-1 Replacement Guaranteed Specifications* From -54°C to +85°C _ Frequency Range RF, LO Ports
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OCR Scan
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PDF
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MD-410
MCL SRA-1
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MCL RMS-2
Abstract: MCL RMS-2 mixer
Text: I t •1 MODEL DOUBLE BALANCED MIXER M D -456 RF, LO 5-1000 MHz IF DC-1000 MHz LO Power +7 dBm Surface Mount MCL Model RMS-2 Replacement Guaranteed Specifications* From -55°C to +85°C _ Frequency Range RF, LO Ports IF Port Conversion Loss
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OCR Scan
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PDF
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DC-1000
MD-456
MCL RMS-2
MCL RMS-2 mixer
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MD-402
Abstract: MCL 402 tfm-4
Text: Jf DOUBLE BALANCED MIXER MODEL MD-402 RF, LO 5-1250 MHz IF DC-1250 MHz LO Power +7 dBm Half Relay Header MCL Model TFM-4 Replacement Guaranteed Specifications* From -54°C to +85°C Frequency Range Conversion Loss Isolation RF, LO Ports IF Port 5 -1250 MHz
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OCR Scan
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PDF
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MD-402
DC-1250
MD-402
MCL 402
tfm-4
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mcl sbl-1
Abstract: mcl sbl-1 MIXER MCL 1 SBL-1 SBL-1 pin connection Anzac 312 mcl mixer MD-426 mcl sbl1
Text: MODEL DOUBLE BALANCED MIXER M D -426 RF, LO 1 - 500 MHz IF DC - 500 MHz LO Power +7 dBm Relay Header Low Cost MCL Model SBL-1 Replacement Guaranteed Specifications* From -54°C to +85°C _ Frequency Range RF, LO Ports IF Port Conversion Loss 1 - 10 MHz
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OCR Scan
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PDF
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MD-426
mcl sbl-1
mcl sbl-1 MIXER
MCL 1 SBL-1
SBL-1 pin connection
Anzac 312
mcl mixer
MD-426
mcl sbl1
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MCL25
Abstract: mcl 333
Text: Trimmable Chip Resistors MCL These resistors are tailored to the desired resistance value using the VAG laser and can replace trimmer potentionmeters used on the circuitry which must be stable for a long period once adjusted. Since adjusting process can be automated, the operating cost of your assembly line will be drastically reduced.
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OCR Scan
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PDF
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MCL25
MCL25
MCL18
mcl 333
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MCL SBL-1X
Abstract: mcl sbl-1 MIXER SBL-1X D427 mcl 427 MCL SBL -1X D-427
Text: It •I MODEL DOUBLE BALANCED MIXER M D-427 RF, LO 10 - 1000 MHz IF 5 - 500 MHz .si LO Power +7 dBm Relay Header Low Cost MCL Model SBL-1X Replacement Guaranteed Specifications* From -54°C to +85°C _ Frequency Range RF, LO Ports IF Port Conversion Loss
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OCR Scan
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PDF
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D-427
MD-427
MCL SBL-1X
mcl sbl-1 MIXER
SBL-1X
D427
mcl 427
MCL SBL -1X
D-427
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Untitled
Abstract: No abstract text available
Text: 1 # • 1 MODEL DOUBLE BALANCED MIXER M D -428 RF, LO 1 - 400 MHz; IF DC - 400 MHz LO Power +7 dBm Relay Header Low Cost MCL Model SBL-1-1 Replacement Guaranteed Specifications* From -54°C to +85°C 1 - 400 MHz DC - 400 MHz Frequency Range RF, LO Ports
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OCR Scan
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PDF
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MD-428
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MCL18
Abstract: No abstract text available
Text: Trïmmable Chip Resistors MCL These resistors are tailored to the desired resistance value using the YAG laser and can replace trimmer potentionmeters usee on the circuitry which must be stable for a long p eio d once adjusted. Since adjusting process can be autom ated, the operating cost of your assembly line will be drastically reduced.
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OCR Scan
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PDF
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MCL18
MCL25
MCL18
MCL25
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TC55YD1837YB-333
Abstract: daj 8P CQ245
Text: TOSHIBA TC55YD1837YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 524,288-WORD BY 36-BIT SYNCHRONOUS STATIC RAM SILICON GATE CMOS SigmaRAM, 21x1 Dp DESCRIPTION The TC55YD1837YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory
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OCR Scan
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PDF
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TC55YD1837YB-333
288-WORD
36-BIT
TC55YD1837YB
368-bit
-602VOa-O
VBIHS01
daj 8P
CQ245
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TENTATIVE TC55YD1873YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 262,144-WORD BY 72-BIT SYNCHRONOUS STATIC RAM SILICON GATE CMOS SigmaRAM, 21x1 Dp DESCRIPTION The TC55YD1873YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory
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OCR Scan
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PDF
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TC55YD1873YB-333
144-WORD
72-BIT
TC55YD1873YB
368-bit
C-BGA209-1422-1
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TENTATIVE TC55YD1819YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 1,048,576-WORD BY 18-BIT SYNCHRONOUS STATIC RAM SILICON GATE CMOS SigmaRAM, 21x1 Dp DESCRIPTION The TC55YD1819YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory
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OCR Scan
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PDF
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TC55YD1819YB-333
576-WORD
18-BIT
TC55YD1819YB
368-bit
C-BGA209-1422-1
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TC55YD1837YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 524,288-WORD BY 36-BIT SYNCHRONOUS STATIC RAM SILICON GATE CMOS SigmaRAM, 21x1 Dp DESCRIPTION The TC55YD1837YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory
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OCR Scan
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PDF
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TC55YD1837YB-333
288-WORD
36-BIT
TC55YD1837YB
368-bit
C-BGA209-1422-1
15lsl
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TENTATIVE TC55YD1837YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 524,288-WORD BY 36-BIT SYNCHRONOUS STATIC RAM SILICON GATE CMOS SigmaRAM, 21x1 Dp DESCRIPTION The TC55YD1837YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory
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OCR Scan
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PDF
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TC55YD1837YB-333
288-WORD
36-BIT
TC55YD1837YB
368-bit
C-BGA209-1422-1
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TC55YD1873YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 262,144-WORD BY 72-BIT SYNCHRONOUS STATIC RAM SILICON GATE CMOS SigmaRAM, 21x1 Dp DESCRIPTION The TC55YD1873YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory
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OCR Scan
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PDF
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TC55YD1873YB-333
144-WORD
72-BIT
TC55YD1873YB
368-bit
C-BGA209-1422-1
15lsl
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TC55YD1819YB-333
Abstract: No abstract text available
Text: T O S H IB A TENTATIVE TC55YD1819YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 1,048,576-WORD BY 18-BIT SYNCHRONOUS STATIC RAM SILICON GATE CMOS SigmaRAM, 21x1 Dp DESCRIPTION The TC55YD1819YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory
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OCR Scan
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PDF
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TC55YD1819YB-333
576-WORD
18-BIT
TC55YD1819YB
368-bit
C-BGA209-1422-1
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qcb 4l
Abstract: No abstract text available
Text: TO SH IB A TENTATIVE TC55YD1837YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 524,288-WORD BY 36-BIT SYNCHRONOUS STATIC RAM DESCRIPTION SILICON GATE CMOS SigmaRAM, 21x1 Dp The TC55YD1837YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory
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OCR Scan
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PDF
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TC55YD1837YB-333
288-WORD
36-BIT
TC55YD1837YB
368-bit
C-BGA209-1422-1
qcb 4l
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