Untitled
Abstract: No abstract text available
Text: GN4121 x1 Lane PCI Express to Local Bridge Data Sheet GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 www.gennum.com 1 of 30 Proprietary & Confidential Revision History Version ECR 152184 Date June 2009 Changes and Modifications Became Data Sheet.
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GN4121
GN4121
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PDF
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GN4124
Abstract: GN412x PCIe phy C4 to BGA E15 52624 GN4121 GN4124-CBE3
Text: GN4124 x4 Lane PCI Express to Local Bridge Data Sheet GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 - 1 May 2009 www.gennum.com 1 of 31 Proprietary & Confidential Revision History Version ECR Date Changes and Modifications 2 151915 May 2009 Created new document describing functionality and the register map for GN4124 &
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GN4124
GN4124
GN4121
GN412x
PCIe phy
C4 to BGA
E15 52624
GN4124-CBE3
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PDF
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FBG676
Abstract: XC7A200T-2-FBG676
Text: Artix-7 FPGA AC701 Evaluation Kit Vivado Design Suite 2012.4 Getting Started Guide UG967 (v1.0) January 10, 2013 0402936-01 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum
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AC701
UG967
2002/96/EC
FBG676
XC7A200T-2-FBG676
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PDF
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Untitled
Abstract: No abstract text available
Text: 32-Lane 8-Port PCIe Gen2 System Interconnect Switch 89HPES32NT8BG2 Datasheet ® Device Overview • All BARs support 32/64-bit base and limit address translation • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers
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32-Lane
89HPES32NT8BG2
32/64-bit
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89H32NT8
Abstract: 89H32NT8BG2
Text: 32-Lane 8-Port PCIe Gen2 System Interconnect Switch 89HPES32NT8BG2 Data Sheet ® Device Overview • All BARs support 32/64-bit base and limit address translation • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers
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32-Lane
89HPES32NT8BG2
PES32NT8BG2
32-lane,
89H32NT8
89H32NT8BG2
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Untitled
Abstract: No abstract text available
Text: 12-Lane 12-Port PCIe Gen2 System Interconnect Switch 89HPES12NT12G2 Data Sheet ® Device Overview Non-Transparent Bridging NTB Support – Supports up to 3 NT endpoints per switch, each endpoint can communicate with other switch partitions or external PCIe
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12-Lane
12-Port
89HPES12NT12G2
32/64-bit
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Untitled
Abstract: No abstract text available
Text: 32-Lane 8-Port PCIe Gen2 System Interconnect Switch 89HPES32NT8BG2 Data Sheet ® Device Overview • All BARs support 32/64-bit base and limit address translation • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers
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32-Lane
89HPES32NT8BG2
32/64-bit
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PDF
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Untitled
Abstract: No abstract text available
Text: 12-Lane 12-Port PCIe Gen2 System Interconnect Switch 89HPES12NT12G2 Datasheet ® Device Overview Non-Transparent Bridging NTB Support – Supports up to 3 NT endpoints per switch, each endpoint can communicate with other switch partitions or external PCIe
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12-Lane
12-Port
89HPES12NT12G2
32/64-bit
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89HPES12NT12G2
Abstract: 89H12NT12G2 89H12NT12 89H12NT12G2ZCHLG
Text: 12-Lane 12-Port PCIe Gen2 System Interconnect Switch 89HPES12NT12G2 Data Sheet ® Device Overview Non-Transparent Bridging NTB Support – Supports up to 3 NT endpoints per switch, each endpoint can communicate with other switch partitions or external PCIe
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12-Lane
12-Port
89HPES12NT12G2
PES12NT12G2
12-lane,
89H12NT12G2
89H12NT12
89H12NT12G2ZCHLG
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89H16NT16G2
Abstract: 89HPES16NT16G2
Text: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions
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16-Lane
16-Port
89HPES16NT16G2
PES16NT16G2
16-lane,
89H16NT16G2
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Untitled
Abstract: No abstract text available
Text: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Datasheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions
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16-Lane
16-Port
89HPES16NT16G2
32/64-bit
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PES16NT16G2
Abstract: 89H16NT16G2
Text: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions
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16-Lane
16-Port
89HPES16NT16G2
PES16NT16G2
16-lane,
89H16NT16G2
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PDF
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89HPES16NT16G2
Abstract: 89hpes16nt16g2 port interconnect 89H16NT16 89H16NT16G2
Text: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions
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16-Lane
16-Port
89HPES16NT16G2
PES16NT16G2
16-lane,
89hpes16nt16g2 port interconnect
89H16NT16
89H16NT16G2
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89H32NT8AG2
Abstract: PES32NT8AG2 89H32NT8AG2ZC 89H32NT8AG2ZCHLGI 89H32NT8AG2ZCHLI 89H32NT8 89HPES32NT8AG2
Text: 32-Lane 8-Port PCIe Gen2 System Interconnect Switch 89HPES32NT8AG2 Data Sheet ® Device Overview • All BARs support 32/64-bit base and limit address translation • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers
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32-Lane
89HPES32NT8AG2
PES32NT8AG2
32-lane,
89H32NT8AG2
89H32NT8AG2ZC
89H32NT8AG2ZCHLGI
89H32NT8AG2ZCHLI
89H32NT8
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FCBGA-484
Abstract: No abstract text available
Text: 32-Lane 8-Port PCIe Gen2 System Interconnect Switch 89HPES32NT8AG2 Data Sheet ® Device Overview • All BARs support 32/64-bit base and limit address translation • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers
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32-Lane
89HPES32NT8AG2
32/64-bit
FCBGA-484
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89H32NT
Abstract: 89H32NT8BG2
Text: 32-Lane 8-Port PCIe Gen2 System Interconnect Switch 89HPES32NT8BG2 Data Sheet ® Device Overview • All BARs support 32/64-bit base and limit address translation • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers
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32-Lane
89HPES32NT8BG2
PES32NT8BG2
32-lane,
89H32NT
89H32NT8BG2
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32x32 DDR2 SDRAM circuit diagram
Abstract: 32x32 DDR2 SDRAM circuit ddr2 ram pcie Design guide AN-431-1
Text: PCI Express-to-DDR2 SDRAM Reference Design Application Note 431 August 2006, ver. 1.0 Introduction The Altera PCI Express-to-DDR2 SDRAM reference design provides a sample interface between the Altera PCI Express MegaCore® function and a 64-bit, 256-MByte DDR2 SDRAM memory. Altera offers this
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64-bit,
256-MByte
32x32 DDR2 SDRAM circuit diagram
32x32 DDR2 SDRAM circuit
ddr2 ram
pcie Design guide
AN-431-1
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Untitled
Abstract: No abstract text available
Text: 24-Lane 6-Port PCIe Gen2 System Interconnect Switch 89HPES24NT6AG2 Data Sheet ® Device Overview • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers – 4 inbound and outbound message registers
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24-Lane
89HPES24NT6AG2
32-bit
64-bit
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Untitled
Abstract: No abstract text available
Text: 24-Lane 6-Port PCIe Gen2 System Interconnect Switch 89HPES24NT6AG2 Datasheet ® Device Overview • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers – 4 inbound and outbound message registers
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24-Lane
89HPES24NT6AG2
32-bit
64-bit
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89H24NT6AG2ZCHLGI
Abstract: PE06RN 89H24NT6 89HPES24NT6AG2 89H24NT6AG2
Text: 24-Lane 6-Port PCIe Gen2 System Interconnect Switch 89HPES24NT6AG2 Data Sheet ® Device Overview • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers – 4 inbound and outbound message registers
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24-Lane
89HPES24NT6AG2
PES24NT6AG2
24-lane,
89H24NT6AG2ZCHLGI
PE06RN
89H24NT6
89H24NT6AG2
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Untitled
Abstract: No abstract text available
Text: 24-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES24NT24G2 Data Sheet ® Device Overview • Movable upstream port within and between switch partitions Non-Transparent Bridging NTB Support – Supports up to 8 NT endpoints per switch, each endpoint can
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24-Lane
24-Port
89HPES24NT24G2
32/64-bit
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Untitled
Abstract: No abstract text available
Text: 32-Lane 8-Port PCIe Gen2 System Interconnect Switch 89HPES32NT8AG2 Data Sheet ® Devic e Ove r vie w • All BARs support 32/64-bit base and limit address translation • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers
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32-Lane
89HPES32NT8AG2
32/64-bit
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PDF
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Untitled
Abstract: No abstract text available
Text: 24-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES24NT24G2 Datasheet ® Device Overview • Movable upstream port within and between switch partitions Non-Transparent Bridging NTB Support – Supports up to 8 NT endpoints per switch, each endpoint can
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24-Lane
24-Port
89HPES24NT24G2
32/64-bit
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89HPES24NT6AG2
Abstract: 89H24NT6AG2 Single Root I/89HPES24NT6AG2
Text: 24-Lane 6-Port PCIe Gen2 System Interconnect Switch 89HPES24NT6AG2 Data Sheet ® Device Overview • Two BARs BAR2 and BAR4 support look-up table based address translation – 32 inbound and outbound doorbell registers – 4 inbound and outbound message registers
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24-Lane
89HPES24NT6AG2
PES24NT6AG2
24-lane,
89H24NT6AG2
Single Root I/89HPES24NT6AG2
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