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    INP13 Price and Stock

    Omega Engineering XIN-P13R-U-125-30-M-TJ-8

    EXOTIC THERMOCOUPLE PROBE, EXTRE
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    DigiKey XIN-P13R-U-125-30-M-TJ-8 Bulk 1
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    Newark XIN-P13R-U-125-30-M-TJ-8 Bulk 1
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    Omega Engineering XIN-P13R-U-125-24-M-Q-18

    VERY HIGH TEMPERATURE EXOTIC THERMOCOUPLE PROBES - Bulk (Alt: XIN-P13R-U-125-24-)
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    Newark XIN-P13R-U-125-24-M-Q-18 Bulk 1
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    Omega Engineering XIN-P13R-U-062-30-M-MQ-6

    Xin-P13R-U-062-30-M-Mq-6 |Omega XIN-P13R-U-062-30-M-MQ-6
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    Omega Engineering XIN-P13R-U-062-30-M-SX-8

    Xin-P13R-U-062-30-M-Sx-8 |Omega XIN-P13R-U-062-30-M-SX-8
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    Omega Engineering XIN-P13R-U-062-30-M-Q-10

    Xin-P13R-U-062-30-M-Q-10 |Omega XIN-P13R-U-062-30-M-Q-10
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    Find more INP13 price and stock on Findchips.com

    INP13 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    AA30

    Abstract: AA34 AB30 M21110 PRBS MSB NCN30
    Text: M21110 17 x 17 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 7 Functional Description - 17 Register Information - 21 Package Information - 28 World Wide Sales Companies - 37 21110-DSH-001-B, 3/27/03


    Original     		PDF M21110 21110-DSH-001-B, AA30 AA34 AB30 M21110 PRBS MSB NCN30

    outp32

    Abstract: M21130 AA30 AA34 AB30 OUTP23 NCN30
    Text: M21130 68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 8 Functional Description - 17 Register Information - 20 Package Information - 25 World Wide Sales Companies - 34 21130-DSH-001-B, 3/27/03


    Original     		PDF M21130 21130-DSH-001-B, outp32 M21130 AA30 AA34 AB30 OUTP23 NCN30

    AD9763

    Abstract: AD9763AST AD9763-EB AWG2021
    Text: a FEATURES 10-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 mHz Output: 75 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation


    Original     		PDF 10-Bit 48-Lead AD9763 10-bit C00617a ST-48) AD9763AST AD9763-EB AWG2021

    48-PIN

    Abstract: AD9709 AD9709AST AD9709-EB AWG2021
    Text: a FEATURES 8-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 MHz Output = 66 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation


    Original     		PDF 48-Lead AD9709 AD9709 C3701 ST-48) 48-PIN AD9709AST AD9709-EB AWG2021

    SMA200UP

    Abstract: AD9767-EBZ
    Text: FEATURES FUNCTIONAL BLOCK DIAGRAM 10-/12-/14-bit dual transmit digital-to-analog converters DACs 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single-resistor gain control


    Original     		PDF 10-/12-/14-Bit, AD9763/AD9765/AD9767 10-/12-/14-bit 48-lead AD9763/ AD9765/ AD9767 SMA200UP AD9767-EBZ

    L510B

    Abstract: L61A L110 L111 l413 l812 L410A L77A L711B L713
    Text: Appl i cat i o n N ot e Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs The recent upsurge of interest in Asynchronous Transfer Mode ATM is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant


    Original     		PDF OUTP10 OUTP11 OUTP12 PADOUTP13 PADOUTP14 PADOUTP15 L510B L61A L110 L111 l413 l812 L410A L77A L711B L713

    SMA200UP

    Abstract: db3p1 INP32 ad8055 T1-1TCUP AD9763 AD9765 AD9767
    Text: 10-/12-/14-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converters AD9763/AD9765/AD9767 FEATURES FUNCTIONAL BLOCK DIAGRAM 10-/12-/14-bit dual transmit digital-to-analog converters DACs 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc


    Original     		PDF 10-/12-/14-Bit, AD9763/AD9765/AD9767 10-/12-/14-bit 48-lead AD9763/AD9765/AD9767 SMA200UP db3p1 INP32 ad8055 T1-1TCUP AD9763 AD9765 AD9767

    AD8047

    Abstract: AD9763 AWG2021
    Text: 10-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converter AD9763 FUNCTIONAL BLOCK DIAGRAM 10-bit dual transmit DAC 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single resistor gain control


    Original     		PDF 10-Bit, AD9763 10-bit 48-lead AD9763ASTRL AD9763ASTZ AD9763ASTZRL1 AD9763-EB AD8047 AD9763 AWG2021

    HDR 2x5

    Abstract: SW-DIP-2 ADP1047 SW-DIP2 hdr_1x3 3224b SPF-26136 HDR 1x3 mma7361 MC9S08MM128
    Text: 5 4 3 2 1 Table of Contents 1 2 3 4 5 6 Revisions TITLE PAGE NOTES MC9S08MM128-MCU OSBDM & PWR CHANGE PERIPHERALS ELEVATOR CONNS Rev Description Date Approved D Release 22-July-10 Michael Norman Garcia Donnie Han Lin Hao Wang D D C C B B Microcontroller Solutions Group


    Original     		PDF MC9S08MM128-MCU 22-July-10 TWR-15 C26GND C31GND C49GND C65GND C81GND TWR-S08MM128 SCH-26136 HDR 2x5 SW-DIP-2 ADP1047 SW-DIP2 hdr_1x3 3224b SPF-26136 HDR 1x3 mma7361 MC9S08MM128

    5 DIGIT dvm

    Abstract: J266 Arcom Arcom Control Systems arcom 12/16 LK1b D-50
    Text: J266 PCAD 12/16H 2192-09062-000-000 PCAD12/16H 16-Channel 12-bit ADC Board Technical Manual Product Information Full information about other Arcom products is available via the Fax-on-Demand System, Telephone Numbers are listed below , or by contacting our WebSite in the UK at: www.arcom.co.uk or in the US at:


    Original     		PDF 12/16H PCAD12/16H 16-Channel 12-bit 50-way EN50081-1: EN50082-1: EN55022 5 DIGIT dvm J266 Arcom Arcom Control Systems arcom 12/16 LK1b D-50

    Untitled

    Abstract: No abstract text available
    Text: 10-/12-/14-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converters AD9763/AD9765/AD9767 FEATURES FUNCTIONAL BLOCK DIAGRAM 10-/12-/14-bit dual transmit digital-to-analog converters DACs 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc


    Original     		PDF 10-/12-/14-Bit, AD9763/AD9765/AD9767 10-/12-/14-bit 48-lead AD9763/ AD9765/ AD9767

    AD9767

    Abstract: AD9767AST AD9767-EB
    Text: a FEATURES 14-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR and IMD: 82 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation


    Original     		PDF 14-Bit 48-Lead AD9767 14-bit updaAD9767 AD9767 AD9767AST AD9767-EB

    C8380

    Abstract: AD804 AD9765 AD97651 AD9765AST AD9765-EB
    Text: a FEATURES 12-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 MHz Output: 75 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation


    Original     		PDF 12-Bit 48-Lead AD9765 12-bit AD9765 C8380 AD804 AD97651 AD9765AST AD9765-EB

    Untitled

    Abstract: No abstract text available
    Text: a Preliminary Technical Data FEATURES 8-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR and IMD: 67 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference


    Original     		PDF 48-Lead AD9709* AD9709 ST-48)

    mod 8 ring counter using JK flip flop

    Abstract: ega to vga circuits q 1257 5v constant power supply lob transistor BR 8772 BR 8050 D 555 design guide BT 4840 CD 4081 Cmos 2 input and gate IC cell phones
    Text: MF1567-01 STANDARD CELL / EMBEDDED ARRAY S1K70000 / S1X70000 Series 5V Tolerant DESIGN GUIDE NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.


    Original     		PDF MF1567-01 S1K70000 S1X70000 mod 8 ring counter using JK flip flop ega to vga circuits q 1257 5v constant power supply lob transistor BR 8772 BR 8050 D 555 design guide BT 4840 CD 4081 Cmos 2 input and gate IC cell phones

    T1-1TCUP

    Abstract: SMA200UP AD9709 DS90LV048B
    Text: 8-Bit, 125 MSPS, Dual TxDAC+ Digital-to-Analog Converter AD9709 FEATURES FUNCTIONAL BLOCK DIAGRAM 8-bit dual transmit digital-to-analog converter DAC 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc Excellent gain and offset matching: 0.1%


    Original     		PDF AD9709 48-lead MS-026-BBC 51706-A ST-48) AD9709ASTZ AD9709ASTZRL1 AD9709-EBZ1 T1-1TCUP SMA200UP AD9709 DS90LV048B

    92x79

    Abstract: 5304 POWER SUPPLY IC driver cicuit diagram transistor BCA 308 computer schematic power supply circuit diagram circuit design truth table NAND gate 74 epson 2480 manual ic configuration of xnor gates PCB design guide
    Text: GATE ARRAY S1L35000 Series DESIGN GUIDE S1L35000 Series DESIGN GUIDE st issue March,2000 D May, 2001 in Japan C A MF924-02 NOTICE No part of this material may be reproduced or duplicated in any from or by any means without the written permission of EPSON. EPSON reserves the right to make changes to this material without


    Original     		PDF S1L35000 MF924-02 92x79 5304 POWER SUPPLY IC driver cicuit diagram transistor BCA 308 computer schematic power supply circuit diagram circuit design truth table NAND gate 74 epson 2480 manual ic configuration of xnor gates PCB design guide

    C3582a-0-2

    Abstract: AD9763 AD9763AST AD9763-EB AWG2021 transmission line transformer
    Text: a FEATURES 10-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR and IMD: 78 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation


    Original     		PDF 10-Bit 48-Lead AD9763 10-bit updaAD9763 AD9763 C3582a-0-2 AD9763AST AD9763-EB AWG2021 transmission line transformer

    INP36

    Abstract: INP30 an555 INP34 INP28 INP14 INP-24 AD9763 AN-555 TP10
    Text: a AN-555 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com Using the AD9709, AD9763, AD9765, AD9767 Dual DAC Evaluation Board By Steve Reine and Dawn Ostenberg GENERAL DESCRIPTION


    Original     		PDF AN-555 AD9709, AD9763, AD9765, AD9767 AD9765 14bits) INP36 INP30 an555 INP34 INP28 INP14 INP-24 AD9763 AN-555 TP10

    PAL16L8 programming algorithm

    Abstract: Intel N85C224 EP330 P85C220 n85c220 PAL20L8 programming specifications 16v8 programming IC PALCE16 palc20r 20V8
    Text: in tj, 85C220/85C224-100, -80 AND -66 FAST REGISTERED SPEED TSU, TSo 8-MACROCELL PLDs These register optimized timing PLDs offer superior design features: • Low-Power, High-Performance Upgrade for SSI/MSI Logic and Bipolar PALs* High-Performance Systems


    OCR Scan     		PDF 85C220/85C224-100, 85C220-100 8SC224-100 85C220 85C224 PAL16L8 programming algorithm Intel N85C224 EP330 P85C220 n85c220 PAL20L8 programming specifications 16v8 programming IC PALCE16 palc20r 20V8

    PAL16L8 programming algorithm

    Abstract: N85C220 85C220 pal16r8 programming algorithm 85C224-66 D85C220-66 intel PLD d85c220 gal 16v8 programming algorithm
    Text: in te i 85C220/85C224-100, -80 AND -66 FAST REGISTERED SPEED TSU, TS0 8-MACROCELL PLDs These register optimized timing PLDs offer superior design features: • Low-Power, High-Performance Upgrade for SSI/MSI Logic and Bipolar PALs* High-Performance Systems


    OCR Scan     		PDF 85C220/85C224-100, 85C220-100 85C224-100 85C220 85C224 PAL16L8 programming algorithm N85C220 pal16r8 programming algorithm 85C224-66 D85C220-66 intel PLD d85c220 gal 16v8 programming algorithm

    Untitled

    Abstract: No abstract text available
    Text: 85C220/85C224-7 AND -10 FAST TpD, HALF-POWER 8-MACROCELL PLDs These Combinatorial Optimized Timing PLDs Offer Superior Design Features: • High-Performance Low-Power Upgrade for -7 and -10 Bipolar/CMOS* PLD’s in High-Performance Systems ■ tpo 7.5 ns, 74 MHz Frequency with


    OCR Scan     		PDF 85C220/85C224-7

    Untitled

    Abstract: No abstract text available
    Text: Ä ID W A M < & g DKlF [^ôiÆ ÂTB©M in te i M85C224 FAST 1-MICRON CHMOS 8-MACROCELL jaPLD Up to 22 Inputs 14 Dedicated & 8 I/O and 8 Outputs High-Performance, Low-Power Upgrade for SSI/MSI Logic and Bipolar PALs* in Intel386 , i486™, i860™, 80960 Series,


    OCR Scan     		PDF M85C224 Intel386â 24-pin

    Untitled

    Abstract: No abstract text available
    Text: inter [P ^ P(U (ST PIH1E¥0EW M85C224 FAST 1-MICRON CHMOS 8-MACROCELL /¿PLD • High-Performance, Low-Power Upgrade for SSI/MSI Logic and Bipolar PLDs in lntel386TM, ¡486 t m , |860 t m , 80960 Series, and Other High-Performance Systems ■ 66 MHz Max Frequency (External


    OCR Scan     		PDF M85C224 lntel386TM, 24-pin Intel386, INP14 INP13 INP12