jedec MS-026 ABA
Abstract: ICS83210AYT MS-026 CY2HH8110 ICS83210 ICS83210AY ICS83210AYLF idt cross TQFP JEDEC tray JEDEC tray standard TQFP
Text: ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83210 is a low skew, 1-to-10 HSTL Fanout ICS Buffer and a member of the HiPerClockS Family HiPerClockS™ of High Performance Clock Solutions from IDT. The class II HSTL outputs are balanced push-pull
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ICS83210
1-TO-10
ICS83210
150MHz
110ps
199707558G
jedec MS-026 ABA
ICS83210AYT
MS-026
CY2HH8110
ICS83210AY
ICS83210AYLF
idt cross
TQFP JEDEC tray
JEDEC tray standard TQFP
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dunlop s 708
Abstract: PTI 30 040 ga AX125 AX2000 CS180 FG256 FG324 FG484 PQ208 M33 thermal fuse
Text: Advanced v1.5 Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO"
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64-bit
608-bit
dunlop s 708
PTI 30 040 ga
AX125
AX2000
CS180
FG256
FG324
FG484
PQ208
M33 thermal fuse
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AA23
Abstract: AD166
Text: EP2A15 Pin Outs. 1.1 Table 1 shows all pins for the EP2A15 672-pin FineLine BGA and the 724-pin ball-grid array BGA Packages. Table 1. EP2A15 Device Pin-Outs I/O & VREF Bank Pin Name/Function Dual-Purpose Function 672-Pin HSTL Class II 724-Pin BGA FineLine BGA
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EP2A15
672-pin
724-pin
672-Pin
TX01p
TX01n
TX02n
AA23
AD166
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HSTL standards
Abstract: JESD8-6 JESD86 XAPP133 HSTL class I
Text: Tech Topics High-Speed Transceiver Logic HSTL Introduction Virtex Series of FPGAs feature the Xilinx exclusive SelectI/O+ technology integrating support for 20 single-ended and differential I/O standards. HSTL is one of the single-ended I/O interfaces supported by every Virtex device, eliminating the need for external level translators
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XAPP133:
com/xapp/xapp133
HSTL standards
JESD8-6
JESD86
XAPP133
HSTL class I
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Untitled
Abstract: No abstract text available
Text: White Paper: Virtex Family R WP156 v1.0 January 2, 2002 High-Speed Transceiver Logic (HSTL) By: Maria George HSTL is a technology-independent interface standard for digital integrated circuits. It is a JEDEC standard developed for voltage scalable and technology independent I/O structures. The I/O
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WP156
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HSTL standards
Abstract: SSTL-18 class sstl 15-V AGX52008-1 APEX20KC
Text: 8. Selectable I/O Standards in Arria GX Devices AGX52008-1.2 Introduction This chapter provides guidelines for using industry I/O standards in Arria GX devices, including: • ■ ■ ■ ■ I/O features I/O standards External memory interfaces I/O banks
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AGX52008-1
HSTL standards
SSTL-18
class sstl
15-V
APEX20KC
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HSTL standards
Abstract: class sstl SSTL-18 EIA standards 15-V SSTL18 JESD89A DDR2 sstl_18 class I
Text: 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices SII52004-4.6 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II and Stratix II GX I/O
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SII52004-4
HSTL standards
class sstl
SSTL-18
EIA standards
15-V
SSTL18
JESD89A
DDR2 sstl_18 class I
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PLL 4046 4011 4017
Abstract: phase angle controller SIII52001-1 SSTL-15 SSTL-18
Text: Stratix III Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V2-1.3 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
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JESD8-15
Abstract: HSTL standards SSTL-18 class 8 date sheet EIA standards 15-V
Text: 10. Selectable I/O Standards in Stratix II and Stratix II GX Devices SII52004-4.6 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II and Stratix II GX I/O
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SII52004-4
JESD8-15
HSTL standards
SSTL-18
class 8 date sheet
EIA standards
15-V
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PLL 4046 4011 4017
Abstract: 5252 F 1107 SSTL-15 SIII52001-1 SSTL-18 4046 PLL Designers Guide 0906NS DDR SDRAM Controller VCO 1430 2230 MHz
Text: 1. Stratix III Device Datasheet: DC and Switching Characteristics SIII52001-1.3 Electrical Characteristics Operating Conditions When Stratix III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible
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SIII52001-1
PLL 4046 4011 4017
5252 F 1107
SSTL-15
SSTL-18
4046 PLL Designers Guide
0906NS
DDR SDRAM Controller
VCO 1430 2230 MHz
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EIA standards 783
Abstract: PLL 566 AGX51004-2 PRBS31 SMPTE292M SSTL-18 din 2982 SMPTE-424M TCO 706
Text: 4. DC and Switching Characteristics AGX51004-2.0 Operating Conditions Arria GX devices are offered in both commercial and industrial grades. Both commercial and industrial devices are offered in –6 speed grade only. This chapter contains the following sections:
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AGX51004-2
EIA standards 783
PLL 566
PRBS31
SMPTE292M
SSTL-18
din 2982
SMPTE-424M
TCO 706
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HSTL standards
Abstract: DDR2 sstl_18 class I 15-V SSTL-18
Text: 4. Selectable I/O Standards in Stratix II & Stratix II GX Devices SII52004-4.5 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II & Stratix II GX I/O
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SII52004-4
HSTL standards
DDR2 sstl_18 class I
15-V
SSTL-18
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HSUL-12
Abstract: SSTL-12 SSTL-125 SSTL-135 SSTL12
Text: 5 I/O Features in Stratix V Devices 2013.06.21 SV51006 Subscribe Feedback This chapter provides details about the features of the Stratix V I/O elements IOEs and how the IOEs work in compliance with current and emerging I/O standards and requirements.
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SV51006
HSUL-12
SSTL-12
SSTL-125
SSTL-135
SSTL12
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HSTL standards
Abstract: 15-V AGX52008-1 APEX20KC SSTL-18
Text: Section IV. I/O Standards This section provides information on Arria GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 8, Selectable I/O Standards in Arria GX Devices
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15-V
Abstract: AGX52008-1 APEX20KC SSTL-18 Teradyne connector 72 pin
Text: Section IV. I/O Standards This section provides information on Arria GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 8, Selectable I/O Standards in Arria GX Devices
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DDR2 sstl_18 class
Abstract: HSTL standards 15-V SSTL-18 N098
Text: Section III. I/O Standards This section provides information on Stratix II single-ended, voltagereferenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 4, Selectable I/O Standards in Stratix II and Stratix II GX
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SSTL "on-chip termination" 1998
Abstract: 15-V SSTL-18 DDR2 SDRAM sstl_18 HSTL standards
Text: Section III. I/O Standards This section provides information on Stratix II single-ended, voltagereferenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 4, Selectable I/O Standards in Stratix II & Stratix II GX
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CMOS applications handbook
Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18
Text: 10. Selectable I/O Standards in Cyclone II Devices CII51010-2.4 Introduction The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18, SSTL-2, and
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CII51010-2
SSTL-18,
CMOS applications handbook
ttl to mini-lvds
EP2C20
EP2C35
EP2C50
SSTL-18
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HSTL standards
Abstract: 15-V SSTL-18
Text: Section IV. I/O Standards This section provides information on Stratix II GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Stratix II and Stratix II GX
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ttl to mini-lvds
Abstract: EP2C5 mini lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18 SSTL IO pad
Text: Section IV. I/O Standards This section provides information on Cyclone II single-ended, voltage referenced, and differential I/O standards. This section includes the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Cyclone II Devices
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565 PLL
Abstract: pll 566 pll 565 ma 8601 pll 565 application HSTL standards Mini Toggle Switch Series 727 CIII52001-1 EP3C10 EP3C120
Text: 1. Cyclone III Device Datasheet: DC and Switching Characteristics CIII52001-1.5 Electrical Characteristics Operating Conditions When Cyclone III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Cyclone III devices,
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CIII52001-1
565 PLL
pll 566
pll 565
ma 8601
pll 565 application
HSTL standards
Mini Toggle Switch Series 727
EP3C10
EP3C120
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SSTL-18
Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 JESD8-15
Text: 10. Selectable I/O Standards in Cyclone II Devices CII51010-2.3 Introduction The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18, SSTL-2, and
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CII51010-2
SSTL-18,
SSTL-18
ttl to mini-lvds
EP2C20
EP2C35
EP2C50
JESD8-15
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Untitled
Abstract: No abstract text available
Text: Delta39K and Quantum38K™ I/O Standards and Configurations Introduction As Delta39K™ and Quantum38K™ approach the densities previously found only in FPGAs, the potential for applications using high-density CPLDs has increased dramatically. In order to support a wide variety of applications from general purpose standard applications to high performance memory and
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Delta39KTM
Quantum38KTM
Quantum38KTM
Delta39K
Quantum38K
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delta39k
Abstract: JESD8-8
Text: PRELIMINARY Delta39K and Quantum38K™ I/O Standards and Configurations Introduction As Delta39K™ and Quantum38K™ approach the densities previously found only in FPGAs, the potential for applications using high-density CPLDs has increased dramatically. In order to support a wide variety of applications from general purpose standard applications to high performance memory and
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Delta39KTM
Quantum38KTM
Quantum38KTM
Delta39K
Quantum38K
JESD8-8
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