higig2 frame format
Abstract: "higig header" EZchip higig2 higig specification verilog code for spi4.2 to fifo higig pause frame marvell 618 datasheet pt36C 0x00900
Text: LatticeSCM XAUI to SPI4.2 July 2008 Reference Design RD1033 Introduction The XAUI to SPI4.2 X2S4 Bridge reference design is a cost-effective system solution for bridging SPI4.2 based network processors and 10G/10G+ Ethernet switching devices. On the XAUI side, the X2S4 optionally supports the
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RD1033
10G/10G+
12Gbps
RD1033.
higig2 frame format
"higig header"
EZchip
higig2
higig specification
verilog code for spi4.2 to fifo
higig pause frame
marvell 618 datasheet
pt36C
0x00900
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higig specification
Abstract: "higig header" BCM56800 bcm pause frame rdbgc0 higig protocol overview IR9216 broadcom bcm BCM0 BCM 10G
Text: LatticeSC/M Broadcom XAUI/HiGig 10 Gbps Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1155 Introduction This technical note describes a physical layer 10-Gigabit Ethernet and HiGig 10 Gbps interoperability test between a LatticeSC/M device and the Broadcom BCM56800 network switch. The test was limited to the physical
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TN1155
10-Gigabit
BCM56800
1-800-LATTICE
higig specification
"higig header"
bcm pause frame
rdbgc0
higig protocol overview
IR9216
broadcom bcm
BCM0
BCM 10G
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higig specification
Abstract: higig2
Text: HiGig Ethernet MAC Page 1 of 2 Home > Products > Intellectual Property > Lattice IP Cores > HiGig Ethernet MAC HiGig MAC Overview The HiGig™ MAC transmits and receives data between a host processor and a HiGig™ / Ethernet network that enables networking customers to add features like quality of service QoS , port trunking,
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SGMII PCIE bridge
Abstract: RGMII to SGMII bridge SGMII RGMII bridge StrataXGS EVALUATION BOARD 88E1111 Marvell 88E1111 mdio 88E1111 jumbo GMII Marvell PHY 88E1111 Datasheet 88e1111 mii fpga ethernet sgmii
Text: f u l l y t e s t e d a n d i n t e r o p e r a b l e Lattice Ethernet Solutions Ready-to-Use Ethernet Portfolio Lattice provides customers with low cost and low power programmable solutions that are ready-to-use right out of the box. A full suite of tested and interoperable solutions is available for Ethernet
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10GbE,
1-800-LATTICE
LatticeMico32,
I0194B
SGMII PCIE bridge
RGMII to SGMII bridge
SGMII RGMII bridge
StrataXGS
EVALUATION BOARD 88E1111
Marvell 88E1111 mdio
88E1111 jumbo GMII
Marvell PHY 88E1111 Datasheet
88e1111 mii
fpga ethernet sgmii
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"higig header"
Abstract: higig specification higig protocol overview TN1154 cx4 to sma BCM56802 higig pause frame ir9216 BROADCOM higig2
Text: LatticeSC/M Broadcom HiGig+ 12 Gbps Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1154 Introduction This technical note describes a physical layer HiGig+ 12 Gbps interoperability test between a LatticeSC/M device and the Broadcom BCM56802 network switch. The test was limited to the physical layer up to XGMII of the 10
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TN1154
BCM56802
1-800-LATTICE
"higig header"
higig specification
higig protocol overview
TN1154
cx4 to sma
higig pause frame
ir9216
BROADCOM
higig2
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higig specification
Abstract: BCM56800 redirectpbmp GTPK 0080D 1000BASE-X 0x00000000001fffff broadcom bcm BCM0
Text: LatticeSC/M 2.5GbE Physical/MAC Layer Interoperability Over CX-4 October 2007 Technical Note TN1164 Introduction This technical note describes a 1000BASE-X physical/MAC layer Gigabit Ethernet GbE interoperability test between a LatticeSC/M device and the Broadcom BCM56800 network switch.
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TN1164
1000BASE-X
BCM56800
1-800-LATTICE
higig specification
redirectpbmp
GTPK
0080D
0x00000000001fffff
broadcom bcm
BCM0
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bcm pause frame
Abstract: BCM56800 1000BASE-X h89e Lattice ECP3 88E111* application cx4 loopback connector redirectpbmp 88E1111 PHY registers map higig pause frame
Text: LatticeECP3 and Broadcom 1 GbE 1000BASE-X Physical/MAC Layer Interoperability July 2010 Technical Note TN1217 Introduction This technical note describes a 1000BASE-X physical/MAC layer Gigabit Ethernet interoperability test between a LatticeECP3 device and the Broadcom BCM56800 network switch.
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1000BASE-X)
TN1217
1000BASE-X
BCM56800
bcm pause frame
h89e
Lattice ECP3
88E111* application
cx4 loopback connector
redirectpbmp
88E1111 PHY registers map
higig pause frame
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higig specification
Abstract: rdbgc0 BCM56580 cx4 to sma GMII layout bcm pause frame 1000BASE-X GR-255 BCM5658 BCM0
Text: LatticeSC/M Broadcom 2.5 GbE Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1156 Introduction This technical note describes a 1000BASE-X physical layer Gigabit Ethernet interoperability test between a LatticeSC/M device and the Broadcom BCM56580 network switch. The test was limited to the physical layer up to
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TN1156
1000BASE-X
BCM56580
1-800-LATTICE
higig specification
rdbgc0
cx4 to sma
GMII layout
bcm pause frame
GR-255
BCM5658
BCM0
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BCM56800
Abstract: higig specification ethernet BCM Gigabit LFSC3GA25E 1000BASE-X higig pause frame cx4 to sma bcm pause frame 1gbps serdes
Text: LatticeSC/M Broadcom 1-Gigabit Ethernet Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1157 Introduction This technical note describes a 1000BASE-X physical layer Gigabit Ethernet interoperability test between a LatticeSC/M device and the Broadcom BCM56800 network switch. The test was limited to the physical layer up to
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TN1157
1000BASE-X
BCM56800
1-800-LATTICE
higig specification
ethernet BCM
Gigabit
LFSC3GA25E
higig pause frame
cx4 to sma
bcm pause frame
1gbps serdes
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h945
Abstract: H944 transistor h945 h965 h946 H948 IR1518 BCM56800 h945 transistor H808
Text: LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability July 2010 Technical Note TN1218 Introduction This technical note describes a Physical/MAC layer 10-Gigabit Ethernet interoperability test between a LatticeECP3 device and the Broadcom BCM56800 network switch. The test exercises the Physical/MAC layer
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TN1218
10-Gigabit
BCM56800
h945
H944
transistor h945
h965
h946
H948
IR1518
h945 transistor
H808
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Broadcom switch cli
Abstract: higig specification Broadcom switch SDK "higig header" marking code BROADCOM BCM5690 sdk BCM5444 BCM5680 BCM95670K8 BCM5690
Text: WHITE PAPER A Scalable Approach to Gigabit Ethernet Switch Design 06/27/02 16215 Alton Parkway • P.O. Box 57013 • Irvine, California 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710 REVISION HISTORY Revision # Date Change Description 567x_569x-WP100-R
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569x-WP100-R
BCM567x/BCM569x
Broadcom switch cli
higig specification
Broadcom switch SDK
"higig header"
marking code BROADCOM
BCM5690 sdk
BCM5444
BCM5680
BCM95670K8
BCM5690
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VCO 100mhz
Abstract: CRC-16 CRC-32 pci express lcrc CRC-16 and CRC-32 Ethernet LFSC115 LFSC15
Text: E x t r e m e P e r f o r m a n c e P r o g r a m m a b l e S y s t e m - ON - A - C h i p LatticeSC FPGA Family Innovation, Integration, and PURESPEED The LatticeSC™ System Chip family of FPGAs combines a high-performance FPGA fabric, 3.8Gbps SERDES and PCS,
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I0181F
VCO 100mhz
CRC-16
CRC-32
pci express lcrc
CRC-16 and CRC-32 Ethernet
LFSC115
LFSC15
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Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor Product Brief Document Number:T4240PB Rev 0, 06/2013 T4240 Product Brief Also supports T4160 Contents 1 Introduction 1 The T4240 QorIQ multicore processor combines 12 dualthreaded e6500 Power Architecture processor cores for a
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T4240PB
T4240
T4160
e6500
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EP2AGX260FF35
Abstract: national linear application notes book ci 740 s rf verilog prbs tranceiver
Text: Arria II GX Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-2.0 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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Untitled
Abstract: No abstract text available
Text: Arria II Device Handbook Volume 1: Device Interfaces and Integration Arria II Device Handbook Volume 1: Device Interfaces and Integration 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-4.0 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.
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9a21
Abstract: No abstract text available
Text: Arria II Device Handbook Volume 1: Device Interfaces and Integration Arria II Device Handbook Volume 1: Device Interfaces and Integration 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-4.4 Document last updated for Altera Complete Design Suite version:
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Abstract: No abstract text available
Text: Arria II Device Handbook Volume 1: Device Interfaces and Integration Arria II Device Handbook Volume 1: Device Interfaces and Integration 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-4.5 Document last updated for Altera Complete Design Suite version:
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stitch images
Abstract: No abstract text available
Text: Arria II GX Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-2.0 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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AIIGX53001-3
Abstract: half bridge converter 2kw higig pause frame EP2AGX65 EP2AGX65DF29 HDTV transmitter receivers block diagram 32-Bit Parallel-IN Serial-OUT Shift Register prbs parity checker and generator SILICON General 741 PMD Motion
Text: Arria II GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-3.0 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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EP2AGX260FF35
Abstract: No abstract text available
Text: Arria II GX Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-2.0 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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Untitled
Abstract: No abstract text available
Text: Arria II GX Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-1.1 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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10-bit-serdes
Abstract: K280A B010011 8HBC D243
Text: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.1 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram
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SIIGX52002-4
8B/10B
10-bit-serdes
K280A
B010011
8HBC
D243
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EP2AGX260EF
Abstract: "switch power supply" handbook
Text: Arria II GX Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-1.1 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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EP2SGX60EF
Abstract: CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer SIIGX52002-4 k307
Text: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.2 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram
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SIIGX52002-4
8B/10B
EP2SGX60EF
CEI 23-16
circuit diagram of PPM transmitter and receiver
CPRI multi rate
HD-SDI over sdh
PRBS10
3G-SDI serializer
k307
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