AS8S512K3
Abstract: No abstract text available
Text: ADVANCED iPEM 64 Mb ASYNC SRAM AS8S2M32PEC 64Mb, 2Mx32 CMOS 3.3V, High Speed Static RAM Integrated Plastic Encapsulated Microcircuit FEATURES DESCRIPTION Integrated Real-Time Memory Array Solution No latency or refresh cycles Parallel Read/Write Interface
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AS8S2M32PEC
2Mx32
M0-47AE
AS8S2M32
AS8S2M32PEC
AS8S512K3
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HIP-66
Abstract: No abstract text available
Text: FLASH AS8FLC1M32 FIGURE 1: PIN ASSIGNMENT Top View Hermetic, Multi-Chip Module (MCM) 32Mb, 1M x 32, 3.0Volt Boot Block FLASH Array Available via Applicable Specifications: • MIL-PRF-38534, Class H FEATURES • • • • • • • • • • • •
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AS8FLC1M32
MIL-PRF-38534,
64Kbyte
1Mx32,
AS8FLC1M32B
HIP-66
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Untitled
Abstract: No abstract text available
Text: SDRAM AS4SD2M32 512K x 32 x 4 Banks 64-Mb PIN ASSIGNMENT (Top View) Synchronous SDRAM 86-Pin TSOPII FEATURES • Full Military temp (-55°C to 125°C) processing available • Configuration: 512K x 32 x 4 banks • Fully synchronous; all signals registered on positive
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AS4SD2M32
64-Mb)
133MHz
TSOPII-86LD
-40oC
-55oC
125oC
AS4SD2M32
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IS61WV51232BLL-10BLI
Abstract: IS61WV51232BLL IS64WV51232BLL IS61WV51232 IS64WV51232BLL-10BA3
Text: IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS 512K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater
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IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
IS61WV51232Axx)
IS61/64WV51232Bxx)
90-ball
IS61WV51232BLL-10BI
IS61WV51232BLL-10BLI
IS61WV51232BLL-10BLI
IS61WV51232BLL
IS64WV51232BLL
IS61WV51232
IS64WV51232BLL-10BA3
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Untitled
Abstract: No abstract text available
Text: CMS4A32LAx–75Ex 128M 4Mx32 Low Power SDRAM Revision 0.6 May. 2007 Rev. 0.6, May. ‘07 CMS4A32LAx–75Ex Document Title 128M(4Mx32) Low Power SDRAM Revision History Revision No. History Draft date Remark Preliminary 0.0 Initial Draft Apr.25th, 2005 0.1
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CMS4A32LAxâ
4Mx32)
160ns
350uA
400uA
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MSM5432128
Abstract: No abstract text available
Text: Pr E2L0045-17-Y1 el im DESCRIPTION The MSM5432126/8 is a new generation Graphics DRAM organized in a 131,072-word ¥ 32-bit configuration. The technology used to fabricate the MSM5432126/8 is OKI's CMOS silicon gate process technology. The device operates with a single 5 V power supply.
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E2L0045-17-Y1
MSM5432126/8
072-word
32-bit
32-bit
MSM5432128
64-pin
SSOP64-P-525-0
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gw 360
Abstract: No abstract text available
Text: EDI2GG432128V 4x128Kx32 Synchronous SRAM CARD EDGE DIMM FEATURES • 4x128Kx32 Synchronous The EDI2GG432128VxxD is a Synchronous SRAM, 60 position Card Edge; DIMM 120 contacts Module, organized as 4x128Kx32. The Module contains four (4) Synchronous Burst Ram Devices,
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EDI2GG432128V
4x128Kx32
EDI2GG432128VxxD
4x128Kx32.
14mmx20mm
EDI2GG432128V95D*
EDI2GG432128V10D*
EDI2GG432128V11D
EDI2GG432128V12D
gw 360
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128*64
Abstract: transistor GW 93 H GW 94 H
Text: EDI2KG464128V 4 Megabyte Synchronous Card Edge DIMM Advanced 4x128Kx64, 3.3V Synchronous Flow-Through Module Features • 4x128Kx64 Synchronous • Flow-Through Architecture • Clock Controlled Registered Bank Enables E1\, E2\, E3, E4\ • Clock Controlled Registered Address
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EDI2KG464128V
4x128Kx64,
4x128Kx64
EDI2KG64128VxxD
01581USA
EDI2KG464128V
128*64
transistor GW 93 H
GW 94 H
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY INFORMATION L9D222G72BG3 2.2 Gb, DDR2, 32 M x 72 Integrated Module IMOD Benefits FEATURES DDR2 SDRAM Data Rate = 800,667,533 and 400Mbps Available in INDUSTRIAL, EXTENDED and MIL-TEMP Package: 16mm x 22mm – 208PBGA, 1.00mm pitch Differential Data Strobe (DQS, DQSx\) per byte
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L9D222G72BG3
400Mbps
208PBGA,
LDS-L9D222G72BG3-B
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CYL008M162FFBU-1ABAI
Abstract: M2A2
Text: PRELIMINARY CYL008M162FFB 128-Mbit 8-Mbit x 16 Low-Power MoBL4 SDRAM Features — Deep Sleep Mode — Self Refresh Mode; standard and low power • Functionality • Temperature: –40°C to +85°C — Internal 4 Bank Operation • 8 mm x 8 mm x 1.0 mm 54-ball 0.8 mm FBGA Package
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CYL008M162FFB
128-Mbit
54-ball
CYL008M162FFB
CYL008M162FFBU-1ABAI
M2A2
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W3J512M32G
Abstract: M41K256M32
Text: W3J512M32G-XBX W3J512M32G T -XB2X W3J512M36/40G(T)-XB3X *PRELIMINARY 2GB – 512M x 32/36/40 DDR3 SDRAM 1.5V – 136/204 PBGA Multi-Chip Package FEATURES BENEFITS DDR3 Data Rate = 800, 1,066, 1333 Mb/s 74% Space savings vs. FBGA Packages:
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W3J512M32G-XBX
W3J512M32G
W3J512M36/40G
x36/40
M41K256M32
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Untitled
Abstract: No abstract text available
Text: W3J512M64K-XPBX W3J512M64K-XLBX *ADVANCED 4GB – 512M x 64 DDR3 SDRAM 1.35V – 543 PBGA Multi-Chip Package FEATURES Address/control terminations included DDR3 Data Rate = 800, 1,066, 1333, 1600* Mb/s Differential clock terminations included
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W3J512M64K-XPBX
W3J512M64K-XLBX
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Untitled
Abstract: No abstract text available
Text: WED9LC6816V 256Kx32 SSRAM/4Mx32 SDRAM – External Memory Solution for Texas Instruments TMS320C6000 DSP FEATURES DESCRIPTION Clock speeds: The WED9LC6816V is a 3.3V, 256K x 32 Synchronous Pipeline SRAM and a 4Mx32 Synchronous DRAM array constructed with
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WED9LC6816V
256Kx32
SSRAM/4Mx32
TMS320C6000
WED9LC6816V
4Mx32
4Mx16
TMS320C6201
TMS320C6201
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M41K256M32
Abstract: No abstract text available
Text: W3J512M32K-XBX W3J512M36K T -XB2X W3J512M36/40K(T)-XB3X *PRELIMINARY 2GB – 512M x 32/36/40 DDR3 SDRAM 1.35V – 136/204 PBGA Multi-Chip Package FEATURES BENEFITS DDR3 Data Rate = 800, 1,066, 1333 Mb/s 74% Space savings vs. FBGA Packages:
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W3J512M32K-XBX
W3J512M36K
W3J512M36/40K
M41K256M32
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Untitled
Abstract: No abstract text available
Text: • P h ilip s S e m ico n d u cto rs ., 1^53^31 DQ24301 IbT APX P rodu ct sp e cifica tio n AUER PHILIPS/DISCRETE b?E D ^ — Schottky barrier diodes FE A T U R E S — BAS70 series Q U IC K R E F E R E N C E DATA • Low leakage current SYM BOL • Low turn-on and high breakdown
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DQ24301
BAS70
LafciS3T31
MHAS03
MRA802
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jeida+dram+88+pin
Abstract: jeida 88 pin jeida dram 88 pin
Text: STI321000C1 -xxVx 88-PIN CARDS 1M X 32 DRAM Card FEATURES • Performance range: ^RAC ^CAC *RC STI321000C1-60Vx 60ns 15ns 110ns STI32100OC1-7OVx 70ns 18ns 130ns STI321000C1-80Vx 80ns 20ns 150ns The Simple Technology STI321000C1 is a 1M bit x 32 Dynamic RAM high density memory card. The Simple Technology
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STI321000C1
STI321000C1-60Vx
STI32100OC1-7OVx
STI321000C1-80Vx
110ns
130ns
150ns
88-PIN
jeida+dram+88+pin
jeida 88 pin
jeida dram 88 pin
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Untitled
Abstract: No abstract text available
Text: STI322000D1 -xxV 72-PIN DIMMS 2M X 32 DRAM DIMM Memory Module FEATURES GENERAL DESCRIPTION • The Simple Technology STI322000D1 is a 2M bits x 32 Dynamic RAM high density memory module. The Simple Technology STI322000D1 consist of four CMOS 2M x 8 DRAMs in 28-pin
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STI322000D1
STI322000D1-60
STI322000D1-80V
110ns
130ns
150ns
72-PIN
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MAS 10 RCD
Abstract: MSM54V32128 1DQ23
Text: O K I Semiconductor_ M SM 54V 32126/8_ 131,072-Word x 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM54V32126/8 is a new generation Graphic D RAM organized in 131,072-word x 32-bit configuration. The technology used to fabricate the MSM54V32126/8 is OKI's CM O S silicon gate
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MSM54V32126/8_
072-Word
32-Bit
MSM54V32126/8
MSM54V32128
MAS 10 RCD
1DQ23
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EZ23
Abstract: MSM5432128
Text: O K I Semiconductor MSM5432126/8_ 131,072-Word x 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5432126/8 is a new generation Graphic DRAM organized in 131,072-word x 32-bit configuration. The technology used to fabricate the MSM5432126/8 is OKI’s CMOS silicon gate
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MSM5432126/8_
072-Word
32-Bit
MSM5432126/8
MSM5432128
EZ23
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Untitled
Abstract: No abstract text available
Text: TOSHIBA THMY721661 BEG-80,-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY721661BEG is a 16,777,216-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59S6408BFT/BFTL DRAMs and an unbuffer on a printed circuit board.
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THMY721661
BEG-80
216-WORD
72-BIT
THMY721661BEG
TC59S6408BFT/BFTL
72-bit
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Untitled
Abstract: No abstract text available
Text: EDI2CG472128V 4 Megabyte Sync/Sync Burst, Dual Key DIMM Advanced 4x128Kx72, 3.3 V Sync/Sync Burst Flow-Through 4x128K x72 Synchronous, S ynchronous Burst The E D I2C G 472128V xxD2 is a S ynchronous/S ynchro Flow-Through A rchitecture nous Burst SRAM , 84 position Dual Key; Double High
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EDI2CG472128V
4x128Kx72,
4x128K
72128V
4x128Kx72.
700P8511111111111
11111111111111II1111111111111111
111111111111111111111111111111111II111111
050TYP.
EDI2CG472128V
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Untitled
Abstract: No abstract text available
Text: ^EDI EDI2KG46464V 2 Megabyte Synchronous Card Edge DIMM ELECTRONIC DESIGNS, IN C ADVANCED 4x64Kx64, 3.3V Module Features Synchronous Flow-Through • 4x64Kx64 Synchronous • Flow-Through A rchitecture • C lock Controlled Registered Bank Enables E1\, Module, organized as 4x64Kx64. The M odule contains
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EDI2KG46464V
4x64Kx64,
4x64Kx64
4x64Kx64.
I2KG46464VxxD
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TH MY7216E1 BEG-80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY7216E1BEG is a 16,777,216-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59S6408BFT DRAMs and an unbuffer on a printed circuit board.
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MY7216E1
BEG-80
216-WORD
72-BIT
THMY7216E1BEG
TC59S6408BFT
72-bit
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Untitled
Abstract: No abstract text available
Text: TO SHIBA THMY641661 BEG-80,-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY641661BEG is a 16,777,216-word by 64-bit synchronous dynamic RAM module consisting of 16 TC59S6408BFT/BFTL DRAMs on a printed circuit board.
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THMY641661
BEG-80
216-WORD
64-BIT
THMY641661BEG
TC59S6408BFT/BFTL
64-bit
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