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    DM74LS1 Search Results

    DM74LS1 Result Highlights (1)

    Part ECAD Model Manufacturer Description Download Buy
    DM74LS154N Rochester Electronics LLC Decoder/Driver, LS Series, Inverted Output, TTL, PDIP24, 0.600 INCH, PLASTIC, MS-011, DIP-24 Visit Rochester Electronics LLC Buy
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    DM74LS1 Price and Stock

    onsemi DM74LS10N

    IC GATE NAND 3CH 3-INP 14MDIP
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    DigiKey DM74LS10N Tube 25
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    onsemi DM74LS14M

    IC INVERT SCHMITT 6CH 1IN 14SOIC
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    DigiKey DM74LS14M Tube 55
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    onsemi DM74LS14N

    IC INVERT SCHMITT 6CH 1IN 14MDIP
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    onsemi DM74LS175N

    IC FF D-TYPE SNGL 4BIT 16DIP
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    DigiKey DM74LS175N Tube 25
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    onsemi DM74LS155N

    IC DECODER/DEMUX 1X2:4 24DIP
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    DigiKey DM74LS155N Tube 25
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    DM74LS1 Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    DM74LS10 Fairchild Semiconductor Triple 3-Input NAND Gate Original PDF
    DM74LS10 Fairchild Semiconductor Triple 3-Input NAND Gates Original PDF
    DM74LS10 National Semiconductor Triple 3-Input NAND Gates Original PDF
    DM74LS10 Unknown TTL Data Book 1980 Scan PDF
    DM74LS107A National Semiconductor Original PDF
    DM74LS107AM National Semiconductor Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs Original PDF
    DM74LS107AM Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    DM74LS107AN National Semiconductor Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs Original PDF
    DM74LS107AN Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    DM74LS107N Unknown TTL Data Book 1980 Scan PDF
    DM74LS109 Fairchild Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs Original PDF
    DM74LS109 Unknown TTL Data Book 1980 Scan PDF
    DM74LS109A Fairchild Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs Original PDF
    DM74LS109A Fairchild Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF
    DM74LS109A National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF
    DM74LS109AJ National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF
    DM74LS109AM Fairchild Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs Original PDF
    DM74LS109AM National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF
    DM74LS109AM Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    DM74LS109AM National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    ...

    DM74LS1 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DM54LS174

    Abstract: 54LS174 54LS174DMQB 54LS174FMQB 54LS175 DM54LS175 DM74LS174 DM74LS175 LS174 LS175
    Text: 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad 175 versions feature complementary


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    PDF 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 54LS174DMQB 54LS174FMQB DM74LS174 DM74LS175 LS174 LS175

    74LS11

    Abstract: MK2870-10N05 DM74LS11 DM74LS11M DM74LS11N M14A MS-001 N14A
    Text: Revised March 2000 DM74LS11 Triple 3-Input AND Gate General Description This device contains three independent gates each of which performs the logic AND function. Ordering Code: Order Number Package Number Package Description DM74LS11M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150 Narrow


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    PDF DM74LS11 DM74LS11M 14-Lead MS-120, DM74LS11N MS-001, 74LS11 MK2870-10N05 DM74LS11 DM74LS11M DM74LS11N M14A MS-001 N14A

    74LS151

    Abstract: DM74LS151 DM74LS151M DM74LS151N DM74LS151SJ M16A M16D MS-001 N16E
    Text: Revised March 2000 DM74LS151 1-of-8 Line Data Selector/Multiplexer General Description Features This data selector/multiplexer contains full on-chip decoding to select the desired data source. The DM74LS151 selects one-of-eight data sources. The DM74LS151 has a


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    PDF DM74LS151 DM74LS151 74LS151 DM74LS151M DM74LS151N DM74LS151SJ M16A M16D MS-001 N16E

    dm74ls174n

    Abstract: No abstract text available
    Text: Revised April 2000 DM74LS174DM74LS175 Hex/Quad D-Type Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad 175 versions feature complementary


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    PDF DM74LS174 DM74LS175 DM74LS174M DM74LS174M DM74LS174MX DM74LS174SJ LS174SJ dm74ls174n

    multiplexer

    Abstract: multiplexer 2to1 selector transistors bipolar DM74150 DM74157 DM74ALS151 DM74ALS153 multiplexer/14052B DM74AS157
    Text: Logic Products by Function Selector Products Logic Product Family Product Description Package Voltage Node DM74150 Bipolar-TTL Data Selector/Multiplexer DIP 5 DM74ALS151 Bipolar-ALS 1 of 8 Line Data Selector/Multiplexer DIP SOIC 5 DM74LS151 Bipolar-LS 1-of-8 Line Data Selector/Multiplexer


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    PDF DM74150 DM74ALS151 DM74LS151 DM74S151 DM74ALS153 DM74LS153 DM74S153 DM74ALS257 DM74AS257 DM74LS257B multiplexer multiplexer 2to1 selector transistors bipolar DM74150 DM74157 DM74ALS151 DM74ALS153 multiplexer/14052B DM74AS157

    54LS138FMQB

    Abstract: DM74LS138N DM74LS138 LS139 DM74LS138 Application 54LS138 54LS138DMQB 54LS138LMQB 54LS139 DM74LS139
    Text: DM74LS138, DM74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be


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    PDF DM74LS138, DM74LS139 LS138 54LS138FMQB DM74LS138N DM74LS138 LS139 DM74LS138 Application 54LS138 54LS138DMQB 54LS138LMQB 54LS139 DM74LS139

    DM74LS166

    Abstract: DM74LS166N DM74LS166WM M16B N16A
    Text: DM74LS166 8-Bit Parallel-In/Serial-Out Shift Registers General Description These parallel-in or serial-in, serial-out shift registers feature gated clock inputs and an overriding clear input. All inputs are buffered to lower the drive requirements to one normalized load, and input clamping diodes minimize switching


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    PDF DM74LS166 DM74LS166 DM74LS166N DM74LS166WM M16B N16A

    DM74LS195AN

    Abstract: DM74LS195A 54LS195A 54LS195ADMQB 54LS195AFMQB 54LS195ALMQB DM74LS195AM E20A J16A M16A
    Text: 54LS195A DM74LS195A 4-Bit Parallel Access Shift Register General Description Features This 4-bit register features parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear All inputs are buffered to lower the input drive


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    PDF 54LS195A DM74LS195A DM74LS195AN DM74LS195A 54LS195ADMQB 54LS195AFMQB 54LS195ALMQB DM74LS195AM E20A J16A M16A

    9821

    Abstract: MAX PLUS II free alu DM74LS181N CIRCUIT DIAGRAM CNA4 C1995 DM54LS181 DM54LS181J DM54LS181W DM74LS181 DM74LS181N
    Text: DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit General Description Features The ’LS181 is a 4-bit Arithmetic Logic Unit ALU which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations Y Y Y Provides 16 arithmetic operations add subtract compare double plus twelve other arithmetic operations


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    PDF DM54LS181 DM74LS181 LS181 DM54LS181J DM54LS181W DM74LS181N 9821 MAX PLUS II free alu DM74LS181N CIRCUIT DIAGRAM CNA4 C1995 DM74LS181 DM74LS181N

    BCD 8421

    Abstract: binary to BCD 8421 BCD 8421 application LS162 MC1455P1S synchronous counter using 4 flip flip 54LS160A 54LS160ADMQB 54LS160AFMQB 54LS160ALMQB
    Text: 54LS160A DM74LS160A 54LS162A DM74LS162A Synchronous Presettable BCD Decade Counters General Description Features The ’LS160 and ’LS162 are high speed synchronous decade counters operating in the BCD 8421 sequence They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus


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    PDF 54LS160A DM74LS160A 54LS162A DM74LS162A LS160 LS162 BCD 8421 binary to BCD 8421 BCD 8421 application MC1455P1S synchronous counter using 4 flip flip 54LS160ADMQB 54LS160AFMQB 54LS160ALMQB

    16-LINE

    Abstract: 4-line to 16-line decoder DM74LS154 DM74LS154N DM74LS154WM M24B MS-011 MS-013 N24A
    Text: Revised July 2003 DM74LS154 4-Line to 16-Line Decoder/Demultiplexer General Description Features Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe


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    PDF DM74LS154 16-Line 4-line-to-16-line 4-line to 16-line decoder DM74LS154 DM74LS154N DM74LS154WM M24B MS-011 MS-013 N24A

    DM74LS154N

    Abstract: No abstract text available
    Text: DM54LS154,DM74LS154 DM54LS154 DM74LS154 4-Line to 16-Line Decoders/Demultiplexers Literature Number: SNOS284A DM54LS154 DM74LS154 4-Line to 16-Line Decoders Demultiplexers General Description Features Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen


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    PDF DM54LS154 DM74LS154 DM74LS154 16-Line SNOS284A DM74LS154N

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74LS138, DM74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applica­ tions, requiring very short propagation delay times. In


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    PDF DM74LS138, DM74LS139 LS138

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74LS136 Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs General Description This device contains four independent gates, each of which perform s the logic exclusive-O R function. Connection Diagram Dual-ln-Line Package


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    PDF DM74LS136 DM74LS136M DM74LS136N S009819 14-Lead

    DM74LS126AN

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74LS126A Quad 3-STATE Buffer Buffer Connection Diagram Dual-ln-Line Package V cc C4 A4 Y4 C3 A3 Y3 DSOO6388-1 Order Number DM74LS126AM or DM74LS126AN See Package Number M14A or N14A Function Table Y = A Inputs Output A C L H L


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    PDF DM74LS126A DM74LS126A 14-Lead DM74LS126AM DM74LS126AN

    dm74ls16

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74LS169A Synchronous 4-Bit Up/Down Binary Counter th e c a rry o u tp u ts . T h e c a rry o u tp u t th u s e n a b le d w ill p ro d u c e T h is s y n c h ro n o u s p re s e tta b le c o u n te r fe a tu re s an in te rn a l


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    PDF DM74LS169A DM74LS169A dm74ls16

    multiplexers 74 LS 150

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74LS157/DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers General Description • S o u rc e p ro g ra m m a b le c o u n te rs T h e s e d a ta s e le c to rs /m u ltip le x e rs c o n ta in in v e rte rs a n d d riv ­


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    PDF DM74LS157/DM74LS158 DM74LS157/DM74LS158 multiplexers 74 LS 150

    74LS165N

    Abstract: 54LS165J
    Text: EM ICONDUCTQ R t DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description This device is an 8-bit serial sh ift register w hich shifts data in the direction of Q A tow ard Q H w hen clocked. Parallel-in ac­ cess is m ade available by eight individual direct d ata inputs,


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    PDF DM74LS165 74LS165N 54LS165J

    DM 0356

    Abstract: ic dM 0365 R dm 0365 r
    Text: S E M IC O N D U C T O R tm DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs General Descriotion w hich increases th e noise im m unity and transform s a slow ly changing input signal to a fa s t changing, jitte r free output. This device contains fo u r independent gates each of which


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    PDF DM74LS132 DS006389-1 DM54LS132J, DM54LS132W, DM74LS132M DM74LS132N DM 0356 ic dM 0365 R dm 0365 r

    DM74LS195AN

    Abstract: DM54LS195AJ DM74LS195AM J16A M16A N16A
    Text: DM54LS195A/DM74LS195A National Semiconductor Corporation DM54LS195A/DM74LS195A 4-Bit Parallel Access Shift Register General Description Features This 4-bit register features parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct over­


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    PDF DM54LS195A/DM74LS195A tl/f/640 DM74LS195AN DM54LS195AJ DM74LS195AM J16A M16A N16A

    dm74 Series

    Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
    Text: LS112A National Semiconductor 54LS112/DM54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and


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    PDF 54LS112/DM54LS112A/DM74LS112A dm74 Series 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM

    54LS181DMQB

    Abstract: 54LS181 54LS181FMQB DM74LS181N J24A N24A W24C MAX PLUS II free alu
    Text: National Semiconductor 54LS181/DM74LS181 4-Bit Arithmetic Logic Unit General Description Features The ’LS181 is a 4-bit Arithmetic Logic Unit ALU which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations.


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    PDF 54LS181/DM74LS181 LS181 54LS/74LS181 TL/F/9821-3 TL/F/9821-4 54LS181DMQB 54LS181 54LS181FMQB DM74LS181N J24A N24A W24C MAX PLUS II free alu

    BCD 8421

    Abstract: binary to BCD 8421 DM74 DM74LS196 DM74LS196M DM74LS196N LS196 M14A N14A
    Text: LS196 National Semiconductor DM74LS196 Presettable Decade Counter General Description Features The ’LS196 decade ripple counter is partitioned into divideby-two and divide-by-five sections which can be combined to count either in BCD 8421 sequence or in a bi-quinary


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    PDF DM74LS196 LS196 TL/F/10179-4 TL/F/10179-5 BCD 8421 binary to BCD 8421 DM74 DM74LS196 DM74LS196M DM74LS196N M14A N14A

    54LS155DMQB

    Abstract: 54LS155FMQB 54LS155LMQB 54LS156DMQB DM54LS155J DM54LS155W DM74LS155M DM74LS155N LS155 LS156
    Text: S E M IC O N D U C T O R tm DM74LS155/DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers General Description Features These TTL circuits feature dual 1 -line-to-4-line d em ultiplex­ ers with individual strobes and com m on binary-address in­ puts in a single 16-pin package. W hen both sections are e n ­


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    PDF DM74LS155/DM74LS156 16-pin 54LS155DMQB 54LS155FMQB 54LS155LMQB 54LS156DMQB DM54LS155J DM54LS155W DM74LS155M DM74LS155N LS155 LS156