DIN 74 AF4 Search Results

DIN 74 AF4 Result Highlights (5)

Part	Manufacturer	Description	Download
CS-DNPDM6MMX2-006	Amphenol Cables on Demand	Amphenol CS-DNPDM6MMX2-006 Premium 6-pin Mini-DIN 6 (MD6) Cable - Mini-DIN 6 Male to Mini-DIN 6 Male 6ft	Datasheet
BPBS8B21P3LF	Amphenol Communications Solutions	Din Accessory Cover
65195-001LF	Amphenol Communications Solutions	Din Accessory Latching Lock
515903532189311LF	Amphenol Communications Solutions	DIN STANDARD POWER
68341-001LF	Amphenol Communications Solutions	Din Accessory C.T.W Housing

DIN 74 AF4 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
PT100 temperature sensor data sheet Abstract: 1-wire sensor Text: CombiTemp Temperature Measuring System Flexible building block concept All wetted parts in acid-proof, stainless steel Some hygienic connections conform to 3-A standards, FDA demands and EHEDG guidelines Flush mounted surface sensor ø80 mm stainless steel housing or	Original	Pt100 Pt1000 UK/2010-02-02 A/DN38 PT100 temperature sensor data sheet 1-wire sensor	PDF
ATMEL08 Abstract: No abstract text available Text: AT40K05, AT40K10, AT40K20, AT40K40 5K – 50K Gates Coprocessor FPGA with FreeRAM DATASHEET Features  Ultra high performance System speeds to 100MHz Array multipliers > 50MHz  10ns flexible SRAM  Internal tri-state capability in each cell  	Original	AT40K05, AT40K10, AT40K20, AT40K40 100MHz 50MHz XC4000 XC5200 ATMEL08	PDF
Untitled Abstract: No abstract text available Text: Pulse Counters and Preset Counters Hour Meters and Timers Frequency Meters and Tachometers Combination Time and Energy Meters Position Displays Process Displays and Controllers for Temperature, Analogue Signals and Strain-Gauge Setpoint Adjuster	Original	L6000 D-78054	PDF
AS 108-120 Abstract: LC1 D12 10 LC1 D18 wiring diagram X4963 LC1 D12 P7 XC3000 XC4000 XC5200 XAPP 017 XC5204 Text: 1 1 XC5200 Series Field Programmable Gate Arrays  December 10, 1997 Version 5.0 1 4* Features Product Specification • • Low-cost, process-optimized, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology	Original	XC5200 XC5202 XC5204 XC5206 XC5210 XC5215 PQ100 VQ100 TQ144 PG156 AS 108-120 LC1 D12 10 LC1 D18 wiring diagram X4963 LC1 D12 P7 XC3000 XC4000 XAPP 017 XC5204	PDF
LC1 D18 wiring diagram Abstract: 8165 input chip chart XC520 XC5200 Family XC5202 XC5204 XC5206 XC5210 XC5215 XC3000 Text: Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology	Original	XC5200 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 LC1 D18 wiring diagram 8165 input chip chart XC520 XC5200 Family XC5202 XC5204 XC5206 XC5210 XC5215 XC3000	PDF
LD7134 Abstract: xcs20xl-tq144 con20a XCS20XLTQ144 AF6 din 74 RT4 RR3 PCI9030 tg08-1505n1 AD 149 AE9 AF3 din 74 standard Text: XRT84L38ES The XRT84L38/XRT83L38 8-Channel T1/E1 Framer/LIU Evaluation Board User’s Manual August 23, 2002 THE XRT84L38/XRT83L38 EVALUATION BOARD USER’S MANUAL 1 XRT84L38ES The XRT84L38/XRT83L38 8-Channel T1/E1 Framer/LIU Evaluation Board User’s Manual	Original	XRT84L38ES XRT84L38/XRT83L38 XRT84L38 XRT83L38 LOOP16 LOOP06 LD7134 xcs20xl-tq144 con20a XCS20XLTQ144 AF6 din 74 RT4 RR3 PCI9030 tg08-1505n1 AD 149 AE9 AF3 din 74 standard	PDF
Untitled Abstract: No abstract text available Text: XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)	Original	XC5200 dedicated24 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240	PDF
X9009 Abstract: r13-112 switch XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 X-9009 XC5215 Text: XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)	Original	XC5200 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 X9009 r13-112 switch XC3000 XC4000 XC5202 XC5204 XC5206 X-9009 XC5215	PDF
XCS20XLTQ144 Abstract: con20a PCI9030 AF4 din 74 RT4 RR3 AF6 din 74 xcs20xl-tq144 10UF LA10 LA12 Text: A B C D DMAD[7:0] LD[7:0] ALE ADS BLASTn LGNT L W _R RDWR- L R ST- RDY_8238 INT_8238n INT_FPGA1 INT_FPGA2 INT_FPGA3 INT_FPGA4 39 40 41 43 44 45 46 48 24 16 27 10 118 25 26 DMAD0 DMAD1 DMAD2 DMAD3 DMAD4 DMAD5 DMAD6 DMAD7 ALE ADS BLASTn LGNT LW_R RDWR- 5 L R ST-	Original	8238n 8438n XRT84L38/XRT83L38 XRT84L18/28/38 PCI9030) XCS20XLTQ144 con20a PCI9030 AF4 din 74 RT4 RR3 AF6 din 74 xcs20xl-tq144 10UF LA10 LA12	PDF
AS 108-120 Abstract: LC1 D12 10 K1882 nec d 882 p datasheet XAPP 138 data XC5200 XC3000 XC4000 XC5202 XC5204 Text: XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)	Original	XC5200 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 XC5210-6PQ208C AS 108-120 LC1 D12 10 K1882 nec d 882 p datasheet XAPP 138 data XC3000 XC4000 XC5202 XC5204	PDF
Untitled Abstract: No abstract text available Text: AT40K05, AT40K10, AT40K20, AT40K40 5K – 50K Gates Coprocessor FPGA with FreeRAM DATASHEET Features  Ultra high performance System speeds to 100MHz Array multipliers > 50MHz  10ns flexible SRAM  Internal tri-state capability in each cell  	Original	AT40K05, AT40K10, AT40K20, AT40K40 100MHz 50MHz XC4000 XC5200	PDF
UPD 552 C Abstract: LC1 D12 P7 XC2000 XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 XC5210 Text: XC5200 Field Programmable Gate Arrays  June 1, 1996 Version 4.0 Preliminary Product Specification Features • Fully supported by XACTstep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	Original	XC5200 PQ100 VQ100 XC5202 XC5204 XC5206 XC5210 XC5215 TQ144 PG156 UPD 552 C LC1 D12 P7 XC2000 XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 XC5210	PDF
LC1 D12 P7 Abstract: XC2000 XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 XC5210 XC5215 Text: XC5200 Field Programmable Gate Arrays  August 6, 1996 Version 4.01 Preliminary Product Specification Features • Fully supported by XACTstep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	Original	XC5200 PQ100 VQ100 XC5202 XC5204 XC5206 XC5210 XC5215 TQ144 PG156 LC1 D12 P7 XC2000 XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 XC5210 XC5215	PDF
xc4000 pin Abstract: 57B8 dsp o212 PQ304 o4413 atmel 144 Text: Features • Ultra High Performance • • • • • • • • – System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10ns Flexible SRAM – Internal 3-State Capability in each Cell FreeRAM – Flexible, Single/Dual Port, Sync/Async 10 ns SRAM	Original	XC4000, XC5200 0896B 01/99/xM xc4000 pin 57B8 dsp o212 PQ304 o4413 atmel 144	PDF

32x32 multiplier verilog code Abstract: W 20 81 210 16X16 32X32 40X40 AT40K05 AT40K10 AT40K20 AT40K40 XC4000 Text: Features • Ultra High Performance • • • • • • • • – System Speeds to 100MHz – Array Multipliers > 50MHz – 10ns Flexible SRAM – Internal 3-State Capability in each Cell FreeRAM – Flexible, Single/Dual Port, Sync/Async 10ns SRAM	Original	100MHz 50MHz XC4000, XC5200 84-Lead, 100-Lead, 144-Lead, 160-Lead, 208-Lead, 225-Lead, 32x32 multiplier verilog code W 20 81 210 16X16 32X32 40X40 AT40K05 AT40K10 AT40K20 AT40K40 XC4000	PDF
AF3 din 74 Abstract: PQFP-128 footprint AT40K AT40K05 AT40K05LV AT40K10 AT40K10LV AT40K20 AT40K20LV AT40K40 Text: Features • Ultra High Performance • • • • • • • • • – System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10 ns Flexible SRAM – Internal Tri-state Capability in Each Cell FreeRAM – Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM	Original	XC4000, XC5200 0896C AF3 din 74 PQFP-128 footprint AT40K AT40K05 AT40K05LV AT40K10 AT40K10LV AT40K20 AT40K20LV AT40K40	PDF
XC5402 Abstract: XC5406 XC5410 Text: f l XILINX XC5400 Hardwire Array Family Preliminary Product Specification Features Description • Mask Programmed version of the XC5200 Field Programmable Gate Array FPGA - Specifically designed for easy XC5200 conversion - Significant cost reduction for high volume	OCR Scan	XC5200 pBG352 BG225 BG352 XC5402 XC5406 XC5410	PDF
gc 7137 ad Abstract: transistor c5200 c5200 transistor TTC 5200 C5200 LC1 D18 P7 HC 148 TRANSISTOR ATIC 164 D2 44 pin Text: £ XILINX XC5200 Series Field Programmable Gate Arrays Novem ber 5, 1998 Version 5.2 Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogram m able architecture - 0.5\|j.m three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)	OCR Scan	XC5200 distribution156 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 gc 7137 ad transistor c5200 c5200 transistor TTC 5200 C5200 LC1 D18 P7 HC 148 TRANSISTOR ATIC 164 D2 44 pin	PDF
XCS200 FPGA Abstract: No abstract text available Text: HXILINX XC5200 Series Field Programmable Gate Arrays December 10, 1997 Version 5.0 Product Specification Features • • Low-cost, process-optimized, register/latch rich, SRAM based reprogrammable architecture - 0.5pm three-layer metal CMOS process technology	OCR Scan	XC5200 XC5202 XC5204 XC5206 XC5210 XC5215 PQ100 VQ100 TQ144 PG156 XCS200 FPGA	PDF
5200 FPGA Abstract: PC8421 Text: SIXILINX* XC5400 Hardwire Array Family Preliminary Product Specification Features Description • Mask Programmed version of the XC 5200 Reid Programmable G ate Array FPGA - Specifically designed for easy XC 5200 conversion - Significant cost reduction for high volume	OCR Scan	BG225 BG352 5200 FPGA PC8421	PDF
GV1 M10 Abstract: TPC842 A7 B14 Text: tlX IU N X XC5200 Field Programmable Gate Arrays August 6,1996 Version 4.01 Preliminary Product Specification Features • Fully supported by XACTstep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	OCR Scan	XC5200 -403C XC5202 XC5204 XC5206 XC5210 XC5215 PQ100 VQ100 TQ144 GV1 M10 TPC842 A7 B14	PDF
Untitled Abstract: No abstract text available Text: JIXILINX XC5200 Field Programmable Gate Arrays June 1, 1996 Version 4.0 Preliminary Product Specification Features • Fully supported by XACTsfep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	OCR Scan	XC5200 PQ100 VQ100 TQ144 PG156 PQ160 TQ176 XC5202 XC5204 XC5206	PDF
ATIC 164 D2 44 pin Abstract: ATIC 164 D2 48 pin ATIC 164 D3 Text: H X IL IN X XC5200 Field Programmable Gate Arrays June 1, 1996 Version 4.0 Prelim inary Product Specification Features • • High-density family of Field-Program m able Gate Arrays (FPGAs) • Design- and process-optimized for low cost - 0.6-nm three-layer metal (TLM) process	OCR Scan	XC5200 PQ100 VQ100 XC5202 XC5204 XC5206 XC5210 XC5215 TQ144 PG156 ATIC 164 D2 44 pin ATIC 164 D2 48 pin ATIC 164 D3	PDF
Untitled Abstract: No abstract text available Text: £ XC5200 Field Programmable Gate Arrays x ilin x August 6,1996 Version 4.01 Preliminary Product Specification Features • Fully supported by XACTsfep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed	OCR Scan	XC5200 PQ100 VQ100 TQ144 PG156 XC5202 XC5204 XC5210 XC5215 PQ160	PDF

DIN 74 AF4 Search Results

DIN 74 AF4 Result Highlights (5)

DIN 74 AF4 Datasheets Context Search

PT100 temperature sensor data sheet

ATMEL08

Untitled

AS 108-120

LC1 D18 wiring diagram

LD7134

Untitled

X9009

XCS20XLTQ144

AS 108-120

Untitled

UPD 552 C

LC1 D12 P7

xc4000 pin

32x32 multiplier verilog code

AF3 din 74

XC5402

gc 7137 ad

XCS200 FPGA

5200 FPGA

GV1 M10

Untitled

ATIC 164 D2 44 pin

Untitled