d3 6440 9
Abstract: rd2c L7583 L8567 PUB43801 T7507 4 channel slic
Text: Product Brief April 1998 T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ +5 V only Low-power, latch-up-free CMOS technology: — 37 mW/channel typical operating power
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T7507
PN98-122ALC
d3 6440 9
rd2c
L7583
L8567
PUB43801
4 channel slic
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Untitled
Abstract: No abstract text available
Text: Features • 8-bit Microcontroller Compatible with MCS 51 Products • Enhanced 8051 Architecture • • • • • – Single-clock Cycle per Byte Fetch – Up to 20 MIPS Throughput at 20 MHz Clock Frequency – Fully Static Operation: 0 Hz to 20 MHz – On-chip 2-cycle Hardware Multiplier
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16x16
256x8
4096x8
32K/64K
3706Câ
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lucent cps 2000
Abstract: d3 6440 9
Text: Preliminary Product Brief, Rev. 1 November 2000 FW802A Low-Power PHY IEEE * 1394a-2000 Two-Cable Transceiver/Arbiter Device Distinguishing Features • Supports connection debounce. ■ Supports multispeed packet concatenation. ■ Supports PHY pinging and remote PHY access
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FW802A
1394a-2000
1394a-2000
PB01-010CMPR-1
lucent cps 2000
d3 6440 9
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FD1S3DX
Abstract: ipad ipad data sheet RAM32X8 scuba orca ap9606
Text: Application Note August 1998 Implementing Single-Clock First-In, First-Out FIFO Buffers in ORCA 2C/TxxA FPGAs Overview Functional Description This application note provides specific details regarding the implementation of first-in, first-out (FIFO) memory blocks using elements from the Lucent
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32-bit
AP97-014FPGA
AP96-063FPGA)
FD1S3DX
ipad
ipad data sheet
RAM32X8
scuba
orca
ap9606
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ci 555
Abstract: ci 7495 54573 OR2C10A CI 576 OR2C40A S240 "Single-Port RAM"
Text: Product Brief April 1999 ORCA Series 2 Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology OR2CxxA , 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology
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16-bit
32-bit
PN99-072FPGA
PN98-018FPGA)
ci 555
ci 7495
54573
OR2C10A
CI 576
OR2C40A
S240
"Single-Port RAM"
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multiplexing demultiplexing e2
Abstract: MSP 105
Text: Product Brief August 2000 STS-1/STS-3 Framer/Multiplexer TMUX Macrocell Functional Description TMUX Introduction The TMUX is a macrocell block that is extractable from the TMXF28155 Super Mapper application specific standard product (ASSP). The TMUX multiplexer block implements SDH/
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TMXF28155
PB00-104NCIP
multiplexing demultiplexing e2
MSP 105
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d3 6440 9
Abstract: No abstract text available
Text: 78A207 MFR1 Receiver DATA SHEET OCTOBER 2005 DESCRIPTION FEATURES The 78A207 is a single-chip, Multi-Frequency MF receiver that can detect all 15 tone-pairs, including ST and KP framing tones. This receiver is intended for use in equal access applications and thus meets
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78A207
d3 6440 9
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lucent m12 timing receiver
Abstract: No abstract text available
Text: Advance Data Sheet August 2000 TRCV0110G 10 Gbits/s Clock Recovery, 1:16 Data Demultiplexer Features • Fully-integrated clock recovery, 1:16 data demultiplexer ■ Supports the standard OC-192/STM-64 data rate of 9.9532 GHz as well as the FEC rate of 10.6642 GHz
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TRCV0110G
OC-192/STM-64
DS00-345HSPL
lucent m12 timing receiver
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Untitled
Abstract: No abstract text available
Text: SQM85N10-10 www.vishay.com Vishay Siliconix Automotive N-Channel 100 V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Halogen-free According to IEC 61249-2-21 Definition 100 RDS(on) () at VGS = 10 V 0.0105 RDS(on) () at VGS = 4.5 V 0.012 ID (A)
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SQM85N10-10
AEC-Q101
2002/95/EC
O-263
O-263
SQM85N10-10-GE3
2011/65/EU
2002/95/EC.
2002/95/EC
2011/65/EU.
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Untitled
Abstract: No abstract text available
Text: SQM100N10-10 www.vishay.com Vishay Siliconix Automotive N-Channel 100 V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY VDS (V) • TrenchFET Power MOSFET • Package with Low Thermal Resistance • AEC-Q101 Qualifiedd 100 RDS(on) () at VGS = 10 V 0.0105
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SQM100N10-10
AEC-Q101
O-263
SQM100N10-10-GE3
2002/95/EC.
2002/95/EC
2011/65/EU.
JS709A
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SQM100N10-10-GE3
Abstract: SQM100N10-10 SQM100N10
Text: SQM100N10-10 www.vishay.com Vishay Siliconix Automotive N-Channel 100 V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY VDS (V) • TrenchFET Power MOSFET • Package with Low Thermal Resistance • AEC-Q101 Qualifiedd 100 RDS(on) () at VGS = 10 V 0.0105
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SQM100N10-10
AEC-Q101
O-263
O-263
SQM100N10-10-GE3
2011/65/EU
2002/95/EC.
2002/95/EC
2011/65/EU.
12-Mar-12
SQM100N10-10-GE3
SQM100N10-10
SQM100N10
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schematic diagram of composite video compression
Abstract: MC44200 schematic diagram vga to S-VIDEO schematic diagram vga to svideo schematic diagram s-video to vga PCT3105CT DB 25 connector female beckman display "ad electronics" schematic diagram vga to composite
Text: September 1998 Application Note 42038 Benchmarking the Performance of the ML6440 INTRODUCTION The ML6440 is a multi-standard 8-bit adaptive digital input comb filter. The 8-bit composite video input can be either NTSC or PAL at CCIR 601 or Square Pixel rates. The
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ML6440
ML6440
schematic diagram of composite video compression
MC44200
schematic diagram vga to S-VIDEO
schematic diagram vga to svideo
schematic diagram s-video to vga
PCT3105CT
DB 25 connector female
beckman display
"ad electronics"
schematic diagram vga to composite
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MCL 0652
Abstract: 342AL PUB43801 T8502 T8503
Text: Data Sheet July 1998 T8502 and T8503 Dual PCM Codecs with Filters Features • Meets or exceeds ITU-T G.711—G.714 requirements and VF characteristics of D3/D4 as per Bellcore PUB43801 ■ +5 V only ■ Two independent channels ■ Pin-selectable receive gain control
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T8502
T8503
711--G
PUB43801)
DS98-342ALC
DS97-205ALC)
MCL 0652
342AL
PUB43801
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TR-NWT-000031
Abstract: GR-506-CORE Telcordia GR-30 GR-506 microcontroller based caller id 0x725-0x754 0xF80 caller id single chip modulo-256 GR30CORE SDMF
Text: User Manual September 2000 T8531 and T8531A Tone Processing Introduction This document specifies the interface between the host microcontroller and the T8531 all references include T8531A unless otherwise specified device for controlling the following embedded tone-processing algorithms:
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T8531
T8531A
T8531
T8531/T8532
GR-506-CORE
MN00-082ALC
MN00-015ALC)
TR-NWT-000031
Telcordia GR-30
GR-506
microcontroller based caller id
0x725-0x754
0xF80
caller id single chip
modulo-256
GR30CORE SDMF
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PUB43801
Abstract: T5504 T7504
Text: Data Sheet March 1999 T7504 and T5504 Quad PCM Codecs with Filters Features • 5 V only ■ Low-power, latch-up-free CMOS technology — 37 mW/channel typical operating power dissipation — 1 mW/channel typical powerdown dissipation ■ Automatic master clock frequency selection
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T7504
T5504
711--G
PUB43801)
DS99-201ALC
DS99-184ALC)
PUB43801
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MPC800
Abstract: mpi interface scuba
Text: Application Note November 1999 ORCA Series 3 Microprocessor Interface ORCA Series 3 Microprocessor Interface Introduction With the increased demand of larger and faster FPGAs, one of the goals of FPGA designers is to utilize as much programmable logic as possible. To
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AP99-050FPGA
MPC800
mpi interface
scuba
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DBM01
Abstract: M2901cem 12-Contact v.23 fsk 1200 bps modem
Text: 73M2901CE V.22bis Single Chip Modem Simplifying System Integration DATA SHEET DS_2901CE_031 April 2009 DESCRIPTION FEATURES The 73M2901CE low speed modem integrates a data pump, controller, and analog front end in a 3.3 V device with a powerful "AT" command host
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73M2901CE
22bis
2901CE
DBM01
M2901cem
12-Contact
v.23 fsk 1200 bps modem
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ATTL7554
Abstract: PUB43801 T5504 T7504 ATTL7551
Text: Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Introduction Lucent Technologies Microelectronics Group’s T7504 and T5504 devices are monolithic, four-channel PCM codecs with filters. These integrated circuits provide the A/D and D/A conversion and the filtering necessary to interface a voice telephone circuit to a timedivision multiplexed system using a standard PCM
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T7504
T5504
T7504
28-pin
T7504)
T5504)
AP00-004ALC
AP96-026ALC)
ATTL7554
PUB43801
ATTL7551
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b1a12
Abstract: M390S2950MTU M390S2950MTU-C1H M390S2950MTU-C1L M390S2950MTU-C75 PC133 registered reference design
Text: Preliminary PC133/100 Low Profile Registered DIMM M390S2950MTU M390S2950MTU SDRAM DIMM 128Mx72 SDRAM DIMM with PLL & Register based on 128Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD FEATURE GENERAL DESCRIPTION • Performance range The Samsung M390S2950MTU is a 128M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M390S2950MTU consists of eighteen CMOS 128Mx4 bit
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PC133/100
M390S2950MTU
M390S2950MTU
128Mx72
128Mx4,
128Mx4
400mil
18bits
b1a12
M390S2950MTU-C1H
M390S2950MTU-C1L
M390S2950MTU-C75
PC133 registered reference design
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M390S2950MT1-C75
Abstract: PC133 registered reference design 128MX4
Text: Preliminary PC133 Registered DIMM M390S2950MT1 M390S2950MT1 SDRAM DIMM 128Mx72 SDRAM DIMM with PLL & Register based on 128Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD FEATURE GENERAL DESCRIPTION • Performance range The Samsung M390S2950MT1 is a 128M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M390S2950MT1 consists of eighteen CMOS 128Mx4 bit
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PC133
M390S2950MT1
M390S2950MT1
128Mx72
128Mx4,
128Mx4
400mil
18bits
M390S2950MT1-C75
PC133 registered reference design
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Receiver RXB6
Abstract: RXB6 txc9 txc7 rxb3 TXC7 oscillator
Text: Advance Data Sheet April 2000 LU5X34F Quad Gigabit Ethernet Transceiver Overview The LU5X34F is a low-cost, low-power quad transceiver. It is used for data transmission over fiber or coaxial media in conformance with IEEE * 802.3z Gigabit Ethernet specification and Fibre Channel
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LU5X34F
X3T11
217-pin
10-bit
DS00-007LAN
Receiver RXB6
RXB6
txc9
txc7
rxb3
TXC7 oscillator
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SL-2203
Abstract: SL2284-20 SL-2264-20.23 SL-2283 SL-2264 LB-602MK2 147 LB-6410 SL-2263 HDSP-5721 HDSP-5723
Text: — 82 — 1 '1 ^ « £ -f t ¥ ft ft & m <Ta = 2 5 ' 0 «ai n ± Se f è •:7 ì , = 2 5 ’C ' Dp v -7 « IE £ n A/mm w I f im A ' I k Kh A') V* V I I f VK im A ') ¡V ’ 2 .2 20 100 40 20 10 2 .2 20 100 3 30 1 .5 10 2 .2 20 10 5 20 1 .5 10 2 .2 20
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HDSP-5721
HDSP-5723
MAN6410
MAN6440
LN524GA
LN524GK
LN524GAS
LN524GKS
LN526GA
LN526GK
SL-2203
SL2284-20
SL-2264-20.23
SL-2283
SL-2264
LB-602MK2 147
LB-6410
SL-2263
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Untitled
Abstract: No abstract text available
Text: XRD6440 X^EXqR 10-Bit 40M SPS CM O S ADC WÆBBWÆBBW* tÆ ÊW Æ ÊÊÊFÆ January 1999-4 FEATURES APPLICATIONS • Video Imaging • Digital Cameras and Camcorders 40 MSPS Conversion Rate • Medical Ultrasound Imaging • On-Chip Track-and-Hold • IR Imaging
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XRD6440
10-Bit
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AD6436
Abstract: AD6438
Text: ANALOG DEVICES DMTCoprocessor for ADSL Chipset AD6436 FEATURES Com ponent in Analog Devices DMT ADSL Chipset— AD20msp910 Designed to ANSI/ETSI T1.413 Cat 1 FDM Suitable fo r CO or Residence (ATU-R and ATU-C) Performs All DMT Functions and Operations: QAM Encoding and Decoding O perations
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AD20msp910
128-Lead
AD6436
20msp910.
AD6435
AD6437
ADSP2183
14-Bit
16-Bit
AD6436.
AD6438
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