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Catalog Datasheet	MFG & Type	Document Tags	PDF
CY7C1461V25 Abstract: CY7C1463V25 CY7C1465V25 Text: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M x 36/2M × 18/512K × 72 common I/O	Original	CY7C1461V25 CY7C1463V25 CY7C1465V25 36/2M 18/512K 133-MHz 36/2M 18/512K 150-MHz CY7C1461V25 CY7C1463V25 CY7C1465V25	PDF
CY7C1444V33 Abstract: CY7C1444V33-300AC CY7C1444V33-300BGC CY7C1444V33-300BZC CY7C1445V33 CY7C1445V33-300AC CY7C1445V33-300BGC Text: CY7C1445V33 CY7C1444V33 PRELIMINARY 1M x 36/2M x 18 Pipelined DCD SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 300, 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.3, 2.7, 3.0, and 3.5 ns	Original	CY7C1445V33 CY7C1444V33 36/2M CY7C1444V33/CY7C1445V33 CY7C1444V33 CY7C1444V33-300AC CY7C1444V33-300BGC CY7C1444V33-300BZC CY7C1445V33 CY7C1445V33-300AC CY7C1445V33-300BGC	PDF
CY7C1441V33 Abstract: CY7C1443V33 Text: CY7C1441V33 CY7C1443V33 CY7C1447V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM Features inputs include all addresses, all data inputs, addresspipelining Chip Enable CE , Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd,	Original	CY7C1441V33 CY7C1443V33 CY7C1447V33 36/2M 18/512K 133-MHz 36/2M 18/512K 150-MHz CY7C1441V33 CY7C1443V33	PDF
SAMPLE HOLD Abstract: CY7C1440V33 Text: 440V33 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY 1M x 36 / 2M x 18 / 512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • inputs include all addresses, all data inputs, address-pipelining Chip Enable CE , burst control inputs (ADSC, ADSP, and	Original	440V33 CY7C1440V33 CY7C1442V33 CY7C1446V33 CY7C1440V33, CY7C1442V33, CY7C1446V33 SAMPLE HOLD CY7C1440V33	PDF
CY7C1371C Abstract: CY7C1371CV25 CY7C1373CV25 CY7C1371 Text: CY7C1373CV25 CY7C1371CV25 PRELIMINARY 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT devices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock	Original	CY7C1373CV25 CY7C1371CV25 36/1M 133-MHz 117-MHz 100-MHz CY7C1371CV25/CY7C1373CV25 CY7C1371C CY7C1371CV25 CY7C1373CV25 CY7C1371	PDF
Untitled Abstract: No abstract text available Text: CY7C1446V25 CY7C1442V25 CY7C1440V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 300,250,200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.3, 2.7, 3.0 and 3.5 ns	Original	CY7C1446V25 CY7C1442V25 CY7C1440V25 36/2M 18/512K CY7C1440V25/CY7C1442V25/CY7C1446V25	PDF
BC165 Abstract: CY7C1460V33 CY7C1462V33 CY7C1462 Text: CY7C1460V33 CY7C1462V33 CY7C1464V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 300, 250, 200, and 167 MHz • Fast access time: 2.3, 2.7, 3.0 and 3.5 ns	Original	CY7C1460V33 CY7C1462V33 CY7C1464V33 36/2M 18/512K CY7C1460V33/CY7C1462V33/CY7C1464V33 BC165 CY7C1460V33 CY7C1462V33 CY7C1462	PDF
CY7C1371 Abstract: CY7C1371C CY7C1371CV25 CY7C1373CV25 Text: CY7C1373CV25 CY7C1371CV25 PRELIMINARY 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT devices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock	Original	CY7C1373CV25 CY7C1371CV25 36/1M 133-MHz 117-MHz 100-MHz CY7C1371CV25/CY7C1373CV25 CY7C1371 CY7C1371C CY7C1371CV25 CY7C1373CV25	PDF
5C75A Abstract: CYM52KQT36AV25 CYM52KQT36AV25-13BBC CYM52KQT36AV25-16BBC 10E131 11J126 Text: CYM52KQT36AV25 ADVANCE INFORMATION 18-Mb Pipelined MCM with QDRTM Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time	Original	CYM52KQT36AV25 18-Mb CYM52KQT36AV25 5C75A CYM52KQT36AV25-13BBC CYM52KQT36AV25-16BBC 10E131 11J126	PDF
Untitled Abstract: No abstract text available Text: CY7C1444V25 CY7C1445V25 PRELIMINARY 1M x 36/2M x 18 Pipelined DCD SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 300, 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.3, 2.7, 3.0 and 3.5 ns	Original	CY7C1444V25 CY7C1445V25 36/2M CY7C1444V25/CY7C1445V25	PDF
CY7C1460V25 Abstract: CY7C1462V25 CY7C1464V25 Text: CY7C1464V25 CY7C1462V25 CY7C1460V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 300,250,200, and 167 MHz • Fast access time: 2.3, 2.7, 3.0 and 3.5 ns	Original	CY7C1464V25 CY7C1462V25 CY7C1460V25 36/2M 18/512K 209-ball BG209 CY7C1460V25 CY7C1462V25 CY7C1464V25	PDF
BB209 Abstract: BB100 BB484 165 BALL FBGA BB42 bb209a 288-ball 676-BALL BB165B Text: Package Diagrams Thin Ball Grid Array Packages 42-Ball Thin Ball Grid Array 6 x 5 x 1.2 mm BB42 51-85139-A 1 Package Diagrams 100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 51-85107-B 2 Package Diagrams 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A 51-85122-*B	Original	42-Ball 100-Ball BB100 165-Ball BB165A BB165B BB165C 172-Ball BB209 BB100 BB484 165 BALL FBGA BB42 bb209a 288-ball 676-BALL BB165B	PDF
CY7C1461V33 Abstract: CY7C1463V33 Text: CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M x 36/2M × 18/512K × 72 common I/O	Original	CY7C1461V33 CY7C1463V33 CY7C1465V33 36/2M 18/512K 133-MHz 36/2M 18/512K 150-MHz CY7C1461V33 CY7C1463V33	PDF
Untitled Abstract: No abstract text available Text: CY7C1447V25 CY7C1443V25 CY7C1441V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM Features inputs are gated by registers controlled by a positiveedge-triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip	Original	CY7C1447V25 CY7C1443V25 CY7C1441V25 36/2M 18/512K 133-MHz x18/512K 150-MHz	PDF