Untitled
Abstract: No abstract text available
Text: LH540206 FEATURES • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags
|
OCR Scan
|
PDF
|
LH540206
IDT7206
IDT7201
LH5496
LH540201
28-Pin,
300-mil
600-mil
LH540206
|
Untitled
Abstract: No abstract text available
Text: LH540206 FEATURES • Fast Access Times: 20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Rags
|
OCR Scan
|
PDF
|
LH540206
IDT7206
IDT7201
LH5496
LH540201
28-Pin,
300-mil
600-mil
LH54020ented
|
Pin and Functionally Compatible with
Abstract: lh540206
Text: PRODUCT PREVIEW V LH540206 CMOS 16384 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35 ns • Fast Fall-Through Time Internal Architecture Based on CMOS Dual-Port SRAM technology • Independently-Synchronized Operation of
|
OCR Scan
|
PDF
|
LH540206
LH540206
Pin and Functionally Compatible with
|
lh540206
Abstract: No abstract text available
Text: LH540206 FEATURES • Fast Access Times: 20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Rags
|
OCR Scan
|
PDF
|
LH540206
IDT7206
IDT7201
LH5496
LH540201
28-Pin,
300-mil
600-mil
LH540206
|