Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    EP2A15 Search Results

    SF Impression Pixel

    EP2A15 Price and Stock

    Rochester Electronics LLC EP2A15F672I8

    IC FPGA 492 I/O 672FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey EP2A15F672I8 Bulk 1
    • 1 $1275.75
    • 10 $1275.75
    • 100 $1275.75
    • 1000 $1275.75
    • 10000 $1275.75
    		Buy Now

    Intel Corporation EP2A15F672C8

    IC FPGA 492 I/O 672FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey EP2A15F672C8 Tray
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Buy Now

    Intel Corporation EP2A15F672C7

    IC FPGA 492 I/O 672FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey EP2A15F672C7 Tray
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Buy Now

    Intel Corporation EP2A15B724C9

    IC FPGA 492 I/O 724BGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey EP2A15B724C9 Tray
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Buy Now

    Rochester Electronics LLC EP2A15B724C8

    IC FPGA 492 I/O 724BGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey EP2A15B724C8 Tray 1
    • 1 $300.45
    • 10 $300.45
    • 100 $300.45
    • 1000 $300.45
    • 10000 $300.45
    		Buy Now
    Find more EP2A15 price and stock on Findchips.com

    EP2A15 Datasheets (22)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    EP2A15-7-BGA724 Altera Programmable Logic Device Original PDF
    EP2A15-7-LBGA672 Altera Programmable Logic Device Original PDF
    EP2A15-8-BGA724 Altera Programmable Logic Device Original PDF
    EP2A15-8-LBGA672 Altera Programmable Logic Device Original PDF
    EP2A15-9-BGA724 Altera Programmable Logic Device Original PDF
    EP2A15-9-LBGA672 Altera Programmable Logic Device Original PDF
    EP2A15B652C7 Altera Integrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array) - IC FPGA Original PDF
    EP2A15B652C8 Altera Integrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array) - IC FPGA Original PDF
    EP2A15B652C9 Altera Integrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array) - IC FPGA Original PDF
    EP2A15B724C7 Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 492 I/O 724BGA Original PDF
    EP2A15B724C7DM Altera Integrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array) - IC FPGA Original PDF
    EP2A15B724C8 Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 492 I/O 724BGA Original PDF
    EP2A15B724C9 Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 492 I/O 724BGA Original PDF
    EP2A15-BGA672 Altera Programmable Logic Device Original PDF
    EP2A15-BGA724 Altera Programmable Logic Device Original PDF
    EP2A15F672C7 Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 492 I/O 672FBGA Original PDF
    EP2A15F672C7AA Altera Integrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array) - IC FPGA Original PDF
    EP2A15F672C7N Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 492 I/O 672FBGA Original PDF
    EP2A15F672C8 Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 492 I/O 672FBGA Original PDF
    EP2A15F672C9 Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 492 I/O 672FBGA Original PDF

    EP2A15 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    AA23

    Abstract: AD166
    Text: EP2A15 Pin Outs. 1.1 Table 1 shows all pins for the EP2A15 672-pin FineLine BGA and the 724-pin ball-grid array BGA Packages. Table 1. EP2A15 Device Pin-Outs I/O & VREF Bank Pin Name/Function Dual-Purpose Function 672-Pin HSTL Class II 724-Pin BGA FineLine BGA


    Original     		PDF EP2A15 672-pin 724-pin 672-Pin TX01p TX01n TX02n AA23 AD166

    AA23

    Abstract: No abstract text available
    Text: EP2A15 I/O Pins ver. 1.0 Table 1 shows all pins for the EP2A15 672-pin FineLine BGA and the 724-pin ball-grid array BGA packages. Table 1. EP2A15 Device Pin-Outs Pin Name/Function I/O & VREF Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8


    Original     		PDF EP2A15 672-pin 724-pin TX01p TX01n TX02n TX02p TX03p AA23

    dct verilog code

    Abstract: EP20K100E-1 EP1S10-C5
    Text: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies IDCT  Low gate count 2-D Inverse Discrete Cosine Transform Megafucntion  Low latency (86 cycles)  Single clock cycle per sample operation Design Quality


    Original     		PDF 16x16 dct verilog code EP20K100E-1 EP1S10-C5

    dct verilog code

    Abstract: EP20K100E-1 2d dct block
    Text: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies DCT  Low gate count 2-D Forward Discrete Cosine Transform Megafunction  Low latency (87 cycles)  Single clock cycle per sample operation Design Quality  Fully compliant with the JPEG


    Original     		PDF 16x16 dct verilog code EP20K100E-1 2d dct block

    EPCS16

    Abstract: epcs128 1064V
    Text: 1. Altera Configuration Devices CF52001-2.4 Introduction During device operation, Altera FPGAs store configuration data in SRAM cells. Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the device powers up. You can configure Stratix® series, Cyclone®


    Original     		PDF CF52001-2 EPC16, 20ction. EPCS16 EPCS64 epcs128 1064V

    7809 voltage regulator datasheet

    Abstract: 7809 voltage regulator voltage regulator 7809 INL03991-02 7809 data sheet national semiconductor embedded system projects pdf free download toshiba web cam TB62705 ST 7809 voltage regulator excalibur Board
    Text: & News Views Second Quarter 2001 Newsletter for Altera Customers Altera Provides the Complete I/O Solution with the New APEX II Device Family Altera introduces the APEXTM II device family— flexible, high-performance, high-density programmable logic devices PLDs that deliver


    Original     		PDF 624-megabit 7809 voltage regulator datasheet 7809 voltage regulator voltage regulator 7809 INL03991-02 7809 data sheet national semiconductor embedded system projects pdf free download toshiba web cam TB62705 ST 7809 voltage regulator excalibur Board

    pin configuration 1K variable resistor

    Abstract: EPC1441 EPC16 EPCS128 EPCS16 EPCS64 EPC8QC100 EPC8QC100 Pinout fpga JTAG Programmer Schematics ic 11105 circuits diagraM
    Text: Configuration Handbook Preliminary Information 101 Innovation Drive San Jose, CA 95134 www.altera.com Config-1.3 September 2007 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original     		PDF

    parallel to serial conversion vhdl IEEE format

    Abstract: altddio_in ARM9 ARM9 based electrical project B956 F1020 epm3064 Synplicity Synplify 2002E
    Text: Quartus II Software Release Notes December 2002 Quartus II version 2.2 This document provides late-breaking information about the following areas of this version of the Altera Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your quartus


    Original     		PDF

    vhdl coding for error correction and detection

    Abstract: vhdl code for 555 EP1S10F780C6 EP2A15F672C7 EP1K100QC208-1 vhdl 4 to 16 decoder 5 to 32 decoder using 3 to 8 decoder vhdl code
    Text: Reed-Solomon Compiler User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Core Version: Document Version: Document Date: 3.3.0 3.3.0 March 2002 Reed-Solomon Compiler MegaCore Function User Guide Copyright  2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all


    Original     		PDF

    AF200

    Abstract: MAC layer sequence number MB250
    Text: POS-PHY Level 4 MegaCore Function POSPHY4 August 2001; ver. 1.00 Data Sheet Introduction Optimized for the Altera APEXTM II device architecture, the POS-PHY level 4 MegaCore® function (POSPHY4) interfaces cell and packet transfers between physical (PHY) and link layer devices. The POSPHY4


    Original     		PDF OC-192, AF200 MAC layer sequence number MB250

    c flex 700

    Abstract: excalibur APEX development board nios apex ep20k400 sopc development board nios development kit cyclone edition EPXA-DEVKIT-XA10D EP20K30E EP20K60E excalibur Board EPF10K50S EPXA10-DEV-BOARD
    Text: Design Software & Development Kit Selector Guide January 2003 Introduction SOPC Builder As FPGAs evolve to include system-level building blocks within the device—such as high-speed I/O circuitry, multi-gigabit transceivers, embedded processors, digital signal processing


    Original     		PDF SG-TOOLS-19 c flex 700 excalibur APEX development board nios apex ep20k400 sopc development board nios development kit cyclone edition EPXA-DEVKIT-XA10D EP20K30E EP20K60E excalibur Board EPF10K50S EPXA10-DEV-BOARD

    tms 3899

    Abstract: lot Code Formats altera cyclone EPC8 bios fail EPM3032 EP1C12F
    Text: Section I. Cyclone FPGA Family Data Sheet This section provides designers with the data sheet specifications for Cyclone devices. The chapters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information,


    Original     		PDF 7000B tms 3899 lot Code Formats altera cyclone EPC8 bios fail EPM3032 EP1C12F

    EPC1213DM883B

    Abstract: EPC8QC100 EPC1213DM883 EPC1064PC8 EP22V10EPC10
    Text: Configuration Devices for February 2002, ver. 12.1 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ Altera Corporation DS-EPROM-12.1 SRAM-Based LUT Devices Serial device family for configuring APEXTM II, APEX 20K including APEX 20K, APEX 20KC, and APEX 20KE , MercuryTM, ACEX® 1K,


    Original     		PDF EPC1213DM883B 5962-9474501MPA) EPC1213DM8 EPC8QC100 EPC1213DM883 EPC1064PC8 EP22V10EPC10

    53413

    Abstract: 58725 632367 594971
    Text: Altera Digital Library CD-ROM December 2002 CD-ADL2002-4.0 Legal Notice This CD ROM contains documentation and other information related to products and services of Altera Corporation “Altera” which is provided as a courtesy to Altera’s customers and potential customers. By copying or using any information contained on this CD ROM, you agree to be bound by the


    Original     		PDF CD-ADL2002-4 Incorpora6596; RE37060; RE35977; 53413 58725 632367 594971

    EP4CE6 package

    Abstract: EP4CE40 Altera EP4CE6 EP4CE55 5M240Z 5M1270Z QFN148 5m570z 5M40 5M80
    Text: Package Information Datasheet for Altera Devices DS-PKG-16.3 This datasheet provides package and thermal resistance information for Altera devices. Package information includes the ordering code reference, package acronym, leadframe material, lead finish plating , JEDEC outline reference, lead


    Original     		PDF DS-PKG-16 EP4CE6 package EP4CE40 Altera EP4CE6 EP4CE55 5M240Z 5M1270Z QFN148 5m570z 5M40 5M80

    RTL code for ethernet

    Abstract: altera ethernet packet generator vhdl code switch layer 2 512x64 vhdl code CRC32 vhdl code for mac interface vhdl code for multistage network CRC-32 block code error management, verilog source code fifo vhdl
    Text: 10 Gigabit Ethernet MAC Core for Altera CPLDs Product Brief Version 1.4 - February 2002 1 Introduction Initially, network managers use 10 Gigabit Ethernet to provide high-speed, local backbone interconnection between large-capacity switches. 10 Gigabit Ethernet enables Internet Service


    Original     		PDF MTIP-10GMAC-lang-arch RTL code for ethernet altera ethernet packet generator vhdl code switch layer 2 512x64 vhdl code CRC32 vhdl code for mac interface vhdl code for multistage network CRC-32 block code error management, verilog source code fifo vhdl

    transistor k 4212

    Abstract: EP1K10 EP1K100 EP1K30 EP1K50 adjustable pwm voltage regulator SLUP183
    Text: Application Note TI Power Solutions Power-Up Altera FPGAs Application Note SLUA278 – October 2002 TI Power Solutions Power-Up Altera FPGAs Sophie Chen Power Supply Control Products ABSTRACT Power requirements and power consumptions for Altera FPGAs, including ACEX 1K, APEX


    Original     		PDF SLUA278 transistor k 4212 EP1K10 EP1K100 EP1K30 EP1K50 adjustable pwm voltage regulator SLUP183

    EPC16

    Abstract: FA12
    Text: APEX II August 2002, ver. 3.0 Features. Data Sheet • ■ ■ Altera Corporation DS-APEXII-3.0 Programmable Logic Device Family Programmable logic device PLD manufactured using a 0.15-µm alllayer copper-metal fabrication process (up to eight layers of metal)


    Original     		PDF

    EPC16

    Abstract: FA12
    Text: APEX II December 2001, ver. 1.3 Features. Data Sheet • ■ ■ Altera Corporation A-DS-APEXII-1.3 Programmable Logic Device Family Programmable logic device PLD manufactured using a 0.15-µm alllayer copper-metal fabrication process (up to eight layers of metal)


    Original     		PDF

    ra1613

    Abstract: FB360 HSTL18 XC2V3000-BG728 XC3S1000-FT256 XC3S200-ft256 X2P376 X2P528 X2P680 BGA 728 35x35 1.27
    Text: XPressArray-II 0.15mm Structured ASIC Data Sheet 1.0 Key Features • Next-generation 0.15mm hybrid structured ASIC • Initializable distributed memory at speeds up to 210MHz • Platform for high-performance 1.5V/1.2V ASICs and FPGAto-ASIC conversions • Configurable signal, core and I/O power supply pin locations


    Original     		PDF 210MHz PCI33, PCI66, ra1613 FB360 HSTL18 XC2V3000-BG728 XC3S1000-FT256 XC3S200-ft256 X2P376 X2P528 X2P680 BGA 728 35x35 1.27

    PQFP 176

    Abstract: 240 pin rqfp drawing EP3C5E144 EP1K50-208 processor cross reference EP3C16F484 MS-034 1152 BGA 84 FBGA thermal TQFP 144 PACKAGE DIMENSION FBGA 1760
    Text: Altera Device Package Information May 2007 version 14.7 Document Revision History Data Sheet Table 1 shows the revision history for this document. Table 1. Document Revision History 1 Date and Document Version May 2007 v14.7 Changes Made ● ● ● ●


    Original     		PDF 144-Pin 100-Pin 256-Pin 780-Pin 256-Pin 68-Pin PQFP 176 240 pin rqfp drawing EP3C5E144 EP1K50-208 processor cross reference EP3C16F484 MS-034 1152 BGA 84 FBGA thermal TQFP 144 PACKAGE DIMENSION FBGA 1760

    HC210

    Abstract: EP20K400E-1
    Text: Baseline ISO/IEC 10918-1 JPEG Compliance  Programmable Huffman Tables JPEG-C Baseline JPEG Codec Megafunction two DC, two AC and  Programmable quantization tables (four)  Up to 4 color components (op- tionally extendable to 255 components)  Supports all possible scan confi-


    Original     		PDF EP1C20-C6 EP2C20-C6 EP2S30-C3 HC210 HC210 EP20K400E-1

    EPC1PI8 N

    Abstract: EPCS128 C-5101-4 epc1213 EPC1PC8 NOR Flash EP20K200E EP20K400E EP20K60E EP2S15
    Text: Section I. FPGA Configuration Devices This section provides information on Altera configuration devices. The following chapters contain information about how to use these devices, feature descriptions, device pin tables, and package diagrams. This section includes the following chapters:


    Original     		PDF EPCS16, EPCS64, EPCS128) EPC16) 20-pin EPC1441LI20 EPC1441 EPC1441PC8 EPC1PI8 N EPCS128 C-5101-4 epc1213 EPC1PC8 NOR Flash EP20K200E EP20K400E EP20K60E EP2S15

    stapl

    Abstract: EPC16 FLEX10KE JESD-71 ieee embedded system projects clr 2996 jam player
    Text: June 2003, ver. 2.0 Introduction Using Jam STAPL for ISP & ICR via an Embedded Processor Application Note 122 Advances in programmable logic devices PLDs have enabled innovative in-system programmability (ISP) and in-circuit reconfigurability (ICR) features. The JamTM Standard Test and Programming Language (STAPL),


    Original     		PDF JESD-71, stapl EPC16 FLEX10KE JESD-71 ieee embedded system projects clr 2996 jam player