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    Untitled

    Abstract: No abstract text available
    Text: CY7C1392JV18/CY7C1992JV18 CY7C1393JV18/CY7C1394JV18 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18- Mbit Density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz Clock for High Bandwidth ■ 2-word Burst for reducing Address Bus Frequency


    Original
    PDF CY7C1392JV18/CY7C1992JV18 CY7C1393JV18/CY7C1394JV18 18-Mbit CY7C1392JV18, CY7C1992JV18, CY7C1393JV18, CY7C1394JV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392JV18, CY7C1992JV18 CY7C1393JV18, CY7C1394JV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18- Mbit Density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz Clock for High Bandwidth ■ 2-word Burst for reducing Address Bus Frequency


    Original
    PDF CY7C1392JV18, CY7C1992JV18 CY7C1393JV18, CY7C1394JV18 18-Mbit CY7C1992JV18, CY7C1394JV18