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    7C1009 Price and Stock

    Infineon Technologies AG CY7C1009B-12VC

    IC SRAM 1MBIT PARALLEL 32SOJ
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1009B-12VC Tube 2,300
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    • 10000 $2.78537
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    Rochester Electronics LLC CY7C1009B-15VC

    IC SRAM 1MBIT PARALLEL 32SOJ
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1009B-15VC Tube 111
    • 1 -
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    • 1000 $2.71
    • 10000 $2.71
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    Infineon Technologies AG CY7C1009B-15VC

    IC SRAM 1MBIT PARALLEL 32SOJ
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1009B-15VC Tube 2,300
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $2.65343
    		Buy Now

    Infineon Technologies AG CY7C1009B-20VC

    IC SRAM 1MBIT PARALLEL 32SOJ
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1009B-20VC Tube 2,300
    • 1 -
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    • 100 -
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    • 10000 $2.52103
    		Buy Now

    Rochester Electronics LLC CY7C1009BN-15VI

    IC SRAM 1MBIT PARALLEL 32SOJ
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1009BN-15VI Bulk 130
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    • 1000 $2.31
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    Find more 7C1009 price and stock on Findchips.com

    7C1009 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    cy7c109bnl

    Abstract: CY7C109BNL-15VC CY7C1009BN CY7C109BN
    Text: CY7C109BN 7C1009BN 128K x 8 Static RAM Functional Description[1] Features • High speed The CY7C109BN/7C1009BN is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable (CE2), an active LOW


    Original     		PDF CY7C109BN CY7C1009BN CY7C109BN/CY7C1009BN cy7c109bnl CY7C109BNL-15VC CY7C1009BN CY7C109BN

    CY7C1009

    Abstract: CY7C109 7C109-25 cypress cy7c109-20zi
    Text: CY7C109 7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW max., 12 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected


    Original     		PDF CY7C109 CY7C1009 CY7C1009 CY7C109 7C109-25 cypress cy7c109-20zi

    CY7C1009V33

    Abstract: CY7C109V33
    Text: 7C1009V33 CY7C109V33 128K x 8 Static RAM Features memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write


    Original     		PDF CY7C1009V33 CY7C109V33 CY7C1009V33 CY7C109V33

    verilog for SRAM 512k word 16bit

    Abstract: CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip
    Text: Product Selector Guide Static RAMs Organization/Density Density X1 X4 4K X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 16K 7C167A 7C168A 7C128A 6116 64K to 72K 7C187 7C164 7C166 7C185 6264 7C182 256K to 288K 7C197 7C194 7C195 7C199 7C1399/V 62256/V 62256V25 62256V18


    Original     		PDF 7C148 7C149 7C150 7C167A 7C168A 7C128A 7C187 7C164 7C166 7C185 verilog for SRAM 512k word 16bit CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip

    CY7C1009D-10VXI

    Abstract: CY7C109D-10VXI a5 gnd
    Text: CY7C109D 7C1009D 1-Mbit 128K x 8 Static RAM Functional Description [1] Features • Pin- and function-compatible with CY7C109B/7C1009B • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10 ns • Low CMOS standby power The CY7C109D/7C1009D is a high-performance CMOS


    Original     		PDF CY7C109D CY7C1009D CY7C109B/CY7C1009B 32-pin 400-Mil CY7C1009D 300-Mil CY7C1009D-10VXI CY7C109D-10VXI a5 gnd

    cy3341

    Abstract: 64K X 4 CACHE SRAM CY7C190 pasic380 cy7c189 palce22v10 programming guide palce16v8 programming algorithm STATIC RAM 6264 vhdl code for 8-bit parity checker 64x18 synchronous sram
    Text: Product Selector Guide Static RAMs Organization/Density Density X1 X4 X4 SIO 7C147 2147 7C123 7C148 7C149 7C150 7C189 7C190 2148 2149 7C122 9122 93422 7C167A 7C168A 7C169A 7C170A 7C171A 7C172A 7C128A 7C187 7C164 7C166 7C161 7C162 7C185 6264 7C182 7C197 7C194


    Original     		PDF 7C147 7C123 7C148 7C149 7C150 7C189 7C190 7C122 7C167A 7C168A cy3341 64K X 4 CACHE SRAM CY7C190 pasic380 cy7c189 palce22v10 programming guide palce16v8 programming algorithm STATIC RAM 6264 vhdl code for 8-bit parity checker 64x18 synchronous sram

    27HC642

    Abstract: 39C10B PAL22V10APC CY2254SC-1 7132SA70 93L422AM 7024S15 7130SA25 7C198-45C 7006S
    Text: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+


    Original     		PDF 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 27S07AC 7C190-25C 27HC642 39C10B PAL22V10APC CY2254SC-1 7132SA70 93L422AM 7024S15 7130SA25 7C198-45C 7006S

    2M X 32 Bits 72-Pin Flash SO-DIMM

    Abstract: AN2131QC Triton P54C SO-DIMM 72pin 32bit 5V 2M AN2131-DK001 AN2131SC vhdl code for pipelined matrix multiplication VIC068A user guide parallel interface ts vhdl 7C037
    Text: GO TO WEB MAIN INDEX 3URGXFW 6HOHFWRU *XLGH Static RAMs Organization/Density Overview Density X1 X4 X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 4 Kb 16 Kb 7C167A 7C168A 7C128A 6116 64 Kb to 72 Kb 7C187 7C164 7C166 7C185 6264 7C182 256 Kb to 288 Kb 7C197 7C194


    Original     		PDF 7C148 7C149 7C150 7C167A 7C168A 7C128A 7C187 7C164 7C166 7C185 2M X 32 Bits 72-Pin Flash SO-DIMM AN2131QC Triton P54C SO-DIMM 72pin 32bit 5V 2M AN2131-DK001 AN2131SC vhdl code for pipelined matrix multiplication VIC068A user guide parallel interface ts vhdl 7C037

    CY7C1009B

    Abstract: CY7C109B
    Text: CY7C109B 7C1009B 128K x 8 Static RAM Features put Enable OE , and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O 0 through I/O 7) is then


    Original     		PDF CY7C109B CY7C1009B CY7C1009B CY7C109B

    San Ace 40

    Abstract: CY7C1009 CY7C109
    Text: 1CY 7C10 9 7C1009 CY7C109 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 853 mW max., 15 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected


    Original     		PDF CY7C1009 CY7C109 San Ace 40 CY7C1009 CY7C109

    CY7C1009

    Abstract: CY7C109
    Text: 009 CY7C109 7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW max., 12 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected


    Original     		PDF CY7C109 CY7C1009 CY7C109, CY7C1009 CY7C109

    CY7C1009V33

    Abstract: CY7C109V33
    Text: fax id: 1089 7C1009V33 CY7C109V33 PRELIMINARY 128K x 8 Static RAM Features memory expansion is provided by an active LOW chip enable CE1 , an active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers. Writing to the device


    Original     		PDF CY7C1009V33 CY7C109V33 CY7C1009V33 CY7C109V33

    CY7C1009BN

    Abstract: CY7C109BN
    Text: CY7C109BN 7C1009BN 128K x 8 Static RAM Functional Description[1] Features • High speed The CY7C109BN/7C1009BN is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable (CE2), an active LOW


    Original     		PDF CY7C109BN CY7C1009BN CY7C109BN/CY7C1009BN CY7C1009BN CY7C109BN

    CY7C109b-20zc

    Abstract: CY7C1009B CY7C109B CY7C109B-15VXC CY7C1009B15VXC
    Text: CY7C109B 7C1009B 128K x 8 Static RAM Functional Description[1] Features • High speed The CY7C109B/7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable (CE2), an active LOW


    Original     		PDF CY7C109B CY7C1009B CY7C109B/CY7C1009B CY7C109b-20zc CY7C1009B CY7C109B CY7C109B-15VXC CY7C1009B15VXC

    EPM5128LC

    Abstract: EPM5128GC epm5064lc-1 EPM5128LC1 59628867809r 5962-8984106LX EPM5128GI 7C19945DMB EPM5130GC-1 5962-8867812rx
    Text: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 5962-8753903LX 5962-8753902LX CY21L49-55C CY21L49-45C CY7C281 CY7C281A 5962-8863701LX 5962-8753902LX CY6116A-45C CY6116A-35C CY7C286 CY27H512 5962-8867003LX 5962-8867002LX CY6116A-55C CY6116A-45C


    Original     		PDF 5962-8753903LX 5962-8863701LX 5962-8867003LX 5962-8867809RX 5962-8867809XX 5962-8867810RX 5962-8867811RX 5962-8867812RX 5962-8871309RX 5962-8871310RX EPM5128LC EPM5128GC epm5064lc-1 EPM5128LC1 59628867809r 5962-8984106LX EPM5128GI 7C19945DMB EPM5130GC-1

    Untitled

    Abstract: No abstract text available
    Text: CY7C109D 7C1009D 1-Mbit 128 K x 8 Static RAM 1-Mbit (128 K × 8) Static RAM Features • Pin- and function-compatible with CY7C109B/7C1009B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA


    Original     		PDF CY7C109D CY7C1009D CY7C109B/CY7C1009B CY7C109D 32-pin 400-Mil CY7C1009D 300-Mil

    Untitled

    Abstract: No abstract text available
    Text: 7C1009: 1 1 -2 5 -9 1 Revision: Monday, January 11,1993 — ^ MAR S 3 1993 PRELIMINARY CYPRESS SEMICONDUCTOR 7C1009 128Kx 8 Static RAM Features Functional Description • Highspeed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 1020 mW


    OCR Scan     		PDF 7C1009: CY7C1009 128Kx 550-mil CY7C1009

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CYPRESS SEMICONDUCTOR Functional Description • High speed T he 7C1009 is a high-perform ance CM O S static R A M organized as 131,072 w ords by 8 bits. Easy m em ory expansion is provided by an active L O W chip enable C E i , an active H IG H chip e n a ble ( C E 2),


    OCR Scan     		PDF CY7C1009 550-mil

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY ÌJS i CYPRESS 128Kx 8 Static RAM Features Functional Description • H igh speed The 7C1009 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable CE] , an active HIGH chip enable (CE2),


    OCR Scan     		PDF 128Kx CY7C1009 550-m

    CY7C109L

    Abstract: CY7C109L-15VI 7C1009 A15C CY7C1009 CY7C109
    Text: CY7C109 7C1009 CYPRESS 128K Features 8 Static RAM able OE , and th re e -sta te drivers. W ritin g to the device is ac­ com p lish ed by takin g C hip Enable O ne (CE-|) and W rite En­ able (W E) inputs LO W and C hip Enable Two (CEg) input HIGH. D ata on the eigh t I/O pins (l/O 0 throu gh l/ 0 7) is then w ritten


    OCR Scan     		PDF CY7C109 CY7C1009 1017mW CY7C109 CY7C1009 128Kx CY7C109L CY7C109L-15VI 7C1009 A15C

    A12CA

    Abstract: No abstract text available
    Text: g # 7C1009 ADVANCED INFORMATION SEMICONDUCTOR 128K x 8 Static RAV RAM Features Functional Description • H ighspeed — U a = 15 ns T he 7C1009 is a high-perform ance CM O S static R A M organized as 131,072 w ords by 8 bits. Easy m em ory expansion is


    OCR Scan     		PDF CY7C1009 7C1009--25 A12CA

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CYPRESS SEMICONDUCTOR Functional Description • High speed T he 7C1009 is a high-perform ance C M O S static R A M organized as 131,072 w ords by 8 bits. E asy m em ory expansion is provided by an active L O W chip enable C E i , an active H IG H chip e n ab le (C E 2),


    OCR Scan     		PDF CY7C1009

    CY7C1009-15VC

    Abstract: No abstract text available
    Text: C Y 7 C 1 0 0 9 C Y 7 C 1 0 9 P Yi. PX :V «*1 128K 8 Static RAM active HIGH chip enable CE2 , an active LOW output enable (UE), and three-state drivers. Writing to the device is accom­ plished by taking chip enable one (CEi) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on


    OCR Scan     		PDF

    AG262

    Abstract: 1009V33-20VC 7C109V33
    Text: fax id: 1089 C'i- 7C1009V33 CY7C109V33 PRELIMINARY 1 2 8 K x 8 S ta tic Features R A M memory expansion is provided by an active LOW chip enable CE-| , an active HIGH chip enable (CE2), an active LOW out­ put enable (UF), and three-state drivers. Writing to the device


    OCR Scan     		PDF CY7C1009V33 CY7C109V33 AG262 1009V33-20VC 7C109V33