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    74LS112 FUNCTION TABLE Search Results

    74LS112 FUNCTION TABLE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TCTH022AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH012BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH012AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TPD4164F Toshiba Electronic Devices & Storage Corporation Intelligent power device / VBB=600V / Iout=2A/ Surface mount type / HSSOP31 Visit Toshiba Electronic Devices & Storage Corporation

    74LS112 FUNCTION TABLE Datasheets Context Search

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    74LS112

    Abstract: TC74HC112AF TC74HC112AFN TC74HC112AP
    Text: TC74HC112AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC112AP,TC74HC112AF,TC74HC112AFN Dual J-K Flip Flop with Preset and Clear The TC74HC112A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology.


    Original     		PDF TC74HC112AP/AF/AFN TC74HC112AP TC74HC112AF TC74HC112AFN TC74HC112A 74LS112 TC74HC112AFN

    74LS112

    Abstract: No abstract text available
    Text: TC74HC112AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC112AP,TC74HC112AF,TC74HC112AFN Dual J-K Flip Flop with Preset and Clear The TC74HC112A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology.


    Original     		PDF TC74HC112AP/AF/AFN TC74HC112AP TC74HC112AF TC74HC112AFN TC74HC112A 74LS112

    Untitled

    Abstract: No abstract text available
    Text: TC74HC112AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC112AP,TC74HC112AF,TC74HC112AFN Dual J-K Flip Flop with Preset and Clear The TC74HC112A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology.


    Original     		PDF TC74HC112AP/AF/AFN TC74HC112AP TC74HC112AF TC74HC112AFN TC74HC112A

    Untitled

    Abstract: No abstract text available
    Text: TC74HC112AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC112AP,TC74HC112AF,TC74HC112AFN Dual J-K Flip Flop with Preset and Clear The TC74HC112A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology.


    Original     		PDF TC74HC112AP/AF/AFN TC74HC112AP TC74HC112AF TC74HC112AFN TC74HC112A

    IC 74HC112

    Abstract: JK flip flop IC diagram 74LS112 JK EDGE TRIGGERED FLIP FLOP 74ls112 pin diagram 74ls112 function table 74HC112 Toggle flip flop IC M54HC112 M54HC112F1R M74HC112
    Text: M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS


    Original     		PDF M54HC112 M74HC112 54/74LS112 M54HC112F1R M74HC112M1R M74HC112B1R M74HC112C1R M54/74HC112 IC 74HC112 JK flip flop IC diagram 74LS112 JK EDGE TRIGGERED FLIP FLOP 74ls112 pin diagram 74ls112 function table 74HC112 Toggle flip flop IC M54HC112 M54HC112F1R M74HC112

    74ls112 pin diagram

    Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
    Text: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,


    OCR Scan     		PDF 1N916, 1N3064, 500ns 500ns 74ls112 pin diagram 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table

    74ls112 pin configuration

    Abstract: 74ls112 function table 74LS112 74S112
    Text: Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,


    OCR Scan     		PDF 74LS112, 1N916, 1N3064, 500ns 500ns 74ls112 pin configuration 74ls112 function table 74LS112 74S112

    74ls112 pin diagram

    Abstract: 74LS112 74ls112 pin configuration 74ls112 function table 74ls112 waveform 74LS 74S112 N74LS112D N74LS112N N74S112D
    Text: 74LS112, S112 S ig n e tic s Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Lo gic P roducts DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set 3d and Reset (Rq) inputs, when LOW,


    OCR Scan     		PDF 74LS112, 1N916, 1N3064, 500ns 74ls112 pin diagram 74LS112 74ls112 pin configuration 74ls112 function table 74ls112 waveform 74LS 74S112 N74LS112D N74LS112N N74S112D

    74ls112 pin diagram

    Abstract: 74ls112 pin configuration 74ls112 function table 74LS112 74S112 74ls112 waveform N74LS112N 1N916 74LS N74LS112D
    Text: Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE T h e '1 1 2 is a d u a l J - K n e g a tiv e e d g e - TY P IC A L f HAX trig g e r e d f lip - f lo p fe a tu r in g in d iv id u a l J,


    OCR Scan     		PDF 74LS112, 1N916, 1N3064, 500ns 74ls112 pin diagram 74ls112 pin configuration 74ls112 function table 74LS112 74S112 74ls112 waveform N74LS112N 1N916 74LS N74LS112D

    74LS412

    Abstract: 74LS41 74ls112n 74LS112D 74ls112 pin configuration 74LS112
    Text: 74LS112, S112 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,


    OCR Scan     		PDF 74LS112, 500ns 500ns 74LS412 74LS41 74ls112n 74LS112D 74ls112 pin configuration 74LS112

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS112 DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS WITH SET AND RESET Features Pin C o n fig u ra tio n • Negative edge-triggering • Diode clamped inputs • Independent input/output terminals for each flip-flop. • Direct set and reset inputs • Q and Q outputs


    OCR Scan     		PDF GD54/74LS112

    74ls112 function table

    Abstract: ph c5V diode 74LS112 J-K flip flop clock inputs
    Text: TC74HC112P/F TC74HC112P/F DUAL J-K FLIP FLOP WITH PRESET AND CLEAR The TC74HC112 is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C 2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.


    OCR Scan     		PDF TC74HC112P/F TC74HC112P/F TC74HC112 58MHz 74ls112 function table ph c5V diode 74LS112 J-K flip flop clock inputs

    74ls112 function table

    Abstract: H R C M F 2J 225
    Text: TOSHIBA TC74HC112AP/AF/AFN Dual J-K Flip-Flop with Preset and Clear The TC74H C 112A is a high speed CMOS DUAL J-K FLIPFLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.


    OCR Scan     		PDF TC74HC112AP/AF/AFN TC74HC112A 67MHz TC74HC/HCT 74ls112 function table H R C M F 2J 225

    74HC112

    Abstract: 74LS112 JK EDGE TRIGGERED FLIP FLOP
    Text: f Z T SGS-THOMSON ^ 7 # « [fM L E O ïM K S M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . HIGHSPEED fMAX = 67 MHz TYP. AT Vcc = 5 V • LOW POWER DISSIPATION Ice = 2 |jA AT T a = 25 ’C ■ HIGH NOISE IMMUNITY V nih = V n il = 28 % V c c (MIN.)


    OCR Scan     		PDF M54HC112 M74HC112 54/74LS112 M54/74HC112 74HC112 74LS112 JK EDGE TRIGGERED FLIP FLOP

    74ls112 pin diagram

    Abstract: No abstract text available
    Text: TOSHIBA LOG IC/MEMOR Y IME 0 I ^0 1 724 0 0 0 1 0 0 3 0 o| — TC74HC112P/F TC 74HC112P/F DUAL J-K FLIP FLOP WITH PRESET AND CLEAR The TC74HC112 is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2M0S technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining


    OCR Scan     		PDF TC74HC112P/F 74HC112P/F TC74HC112 TC74H C112P/F 74ls112 pin diagram

    Untitled

    Abstract: No abstract text available
    Text: / = T ^ 7# M 5 4 H C 1 12 M 7 4 H C 1 12 S G S -T H O M S O N ü M tM U liO T O K S DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX = 67 MHz TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 2 |aA AT T a = 25 "C ■ HIGH NOISE IMMUNITY Vnih = Vnil = 28 % Vcc (MIN.)


    OCR Scan     		PDF 54/74LS112 M54HC112F1R M74HC112B1R M54/74H M54/M74HC112

    74LS112

    Abstract: No abstract text available
    Text: TOSHIBA TC74HC112AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC112AP, TC74HC112AF, TC74HC112AFN DUAL J - K FLIP-FLO P WITH PRESET AND CLEAR The TC74HC112A is a high speed CMOS DUAL J -K FLIP FLOP fabricated with silicon gate C2MOS technology.


    OCR Scan     		PDF TC74HC112AP/AF/AFN TC74HC112AP, TC74HC112AF, TC74HC112AFN TC74HC112A 16PIN DIP16-P-300-2 16PIN 200mil 74LS112

    74hc112

    Abstract: No abstract text available
    Text: M54HC112 M74HC112 SCSTHOMSON m DUAL J-K FLIP FLOP WITH PRESET AND CLEAR a HIGH SPEED fMAX = 59 MHz Typ. at VCC= 5V LOW POWER DISSIPATION lCC = 2 (iA at Ta = 25°C • HIGH NOISE IMMUNITY VNIH = VNIL= 28% Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS


    OCR Scan     		PDF M54HC112 M74HC112 54/74LS112 M54/74HC112 M54HC112/M74HCis M54/74HC112 74hc112

    Untitled

    Abstract: No abstract text available
    Text: SbE D • 7 * ^ 2 3 7 OGB'îflm 2S7 ■ S G T H S G S -T H O M S O N M 5 4 H C Ï 12 LiOT KDD i M 7 4 H C 1 12 6 S-THOMSON ’T-HÙ-ÔT-OT DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ■ HIGH SPEED fMAX = 59 MHz (Typ. at VCC= 5V LOW POWER DISSIPATION Ice = 2 jiA at TA = 25°C


    OCR Scan     		PDF 280/o 54/74LS112 74HC112 S-10216

    74LSOO

    Abstract: PRESET 1M 1S2074 HD74LS112
    Text: H D 74LS112. Dual J-K Negative-edge-triggered Flip-Flops with Preset and Clear •BLOCK D IA G R A M (^) « P IN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Sym bol Item f 'l t 'k C lo c k fre q u e n c y C lo c k H igh min ty p m ax U n it - 30 M Hz


    OCR Scan     		PDF HD74LS112. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO PRESET 1M 1S2074 HD74LS112

    74ls112 function table

    Abstract: No abstract text available
    Text: TOSHIBA TC74HC112AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC112AP, TC74HC112AF, TC74HC112AFN Note The JEDEC SOP (FN) is not available in DUAL J - K FLIP-FLOP WITH PRESET AND CLEAR Japan The TC74HC112A is a high speed CMOS DUAL J - K FLIP


    OCR Scan     		PDF TC74HC112AP/AF/AFN TC74HC112AP, TC74HC112AF, TC74HC112AFN TC74HC112A 16PIN DIP16-P-300-2 16PIN 200mil 74ls112 function table

    74LS112

    Abstract: TC74HC112AF TC74HC112AFN TC74HC112AP 74ls112 function table
    Text: TC74HC112AP/AF/AFN TOSHIBA TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T C 74H C 112A P , T C 74H C 112A F , T C 74H C 112A F N DUAL J - K FLIP-FLO P WITH PRESET AND CLEAR Note The JEDEC SOP (FN) is not available in Japan The TC74HC112A is a high speed CMOS DUAL J -K FLIP


    OCR Scan     		PDF TC74HC112AP/AF/AFN TC74HC112AP, TC74HC112AF, TC74HC112AFN TC74HC112A 16PIN DIP16-P-300-2 75MAX 735TYP 74LS112 TC74HC112AF TC74HC112AFN TC74HC112AP 74ls112 function table

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC74HC112AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC112AP, TC74HC112AF, TC74HC112AFN Note The JEDEC SOP (FN) is not available in DUAL J - K FLIP-FLOP WITH PRESET AND CLEAR Japan The TC74HC112A is a high speed CMOS DUAL J - K FLIP


    OCR Scan     		PDF TC74HC112AP/AF/AFN TC74HC112AP, TC74HC112AF, TC74HC112AFN TC74HC112A 16PIN DIP16-P-300-2 16PIN 200mil

    hc232

    Abstract: No abstract text available
    Text: TC74HC112AP/AF/AFN D U A L J - K F L I P - F L O P WI TH P R E S E T A N D C L E A R The TC74HC112A is a high speed CM O S D U A L J - K F L I P F L O P fab ricate d with silico n g a te C 2 MOS technology. It achieves the high speed operatio n s im ila r to


    OCR Scan     		PDF TC74HC112AP/AF/AFN TC74HC112A HC-232 HC-233 hc232