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Texas Instruments SN74ACT11109D
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Bristol Electronics	SN74ACT11109D		188			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments 74ACT11109D IC,FLIP-FLOP,DUAL,J/K TYPE,ACT-CMOS,SOP,16PIN,PLASTIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Quest Components	74ACT11109D		3,574			1 $1.425 10 $1.425 100 $1.425 1000 $0.6555 10000 $0.5985	Buy Now
Chip 1 Exchange	74ACT11109D		5			1 - 10 - 100 - 1000 - 10000 -	Get Quote

74ACT11109 Datasheets (9)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
74ACT11109		Texas Instruments	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET		Original	PDF
74ACT11109		Texas Instruments	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET		Original	PDF
74ACT11109D		Texas Instruments	DUAL J-Inverted(K) POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET		Original	PDF
74ACT11109D		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF
74ACT11109D		Texas Instruments	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET		Scan	PDF
74ACT11109DR		Texas Instruments	Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset		Original	PDF
74ACT11109N		Texas Instruments	DUAL J-Inverted(K) POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET		Original	PDF
74ACT11109N		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF
74ACT11109N		Texas Instruments	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET		Scan	PDF

74ACT11109 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: 54ACT11109, 74ACT11109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET ăą SCAS451 − FEBRUARY 1987 − REVISED APRIL 1993 • • • 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J	Original	PDF	54ACT11109, 74ACT11109 SCAS451 54ACT11109
54ACT11109 Abstract: 74ACT11109 Text: 54ACT11109, 74ACT11109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET ăą SCAS451 − FEBRUARY 1987 − REVISED APRIL 1993 • • • 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J	Original	PDF	54ACT11109, 74ACT11109 SCAS451 54ACT11109 54ACT11109 74ACT11109
54ACT11109 Abstract: 74ACT11109 Text: 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 • • • 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J 2K 54ACT11109 . . . FK PACKAGE	Original	PDF	54ACT11109, 74ACT11109 SCAS451 54ACT11109 54ACT11109 74ACT11109
Untitled Abstract: No abstract text available Text: 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 • • • 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J 2K 54ACT11109 . . . FK PACKAGE	Original	PDF	54ACT11109, 74ACT11109 SCAS451 54ACT11109
54ACT11109 Abstract: 74ACT11109 D2957 611H Text: _ 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0 0 6 7 — D 2 9 5 7 , F E B R U A R Y 1 9 8 7 — R E V I S E D J A N U A R Y 1 9 9 0 Inputs are TTL-Voltage Compatible 54ACT11109 . . . J P A C K A G E 74ACT11109 . . D O R N P A C K A G E	OCR Scan	PDF	54ACT11109, 74ACT11109 TI0067â D2957, 500-mA 300-mil 54ACT11109 D2957 611H
Untitled Abstract: No abstract text available Text: 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0067— D2957, FEBRUARY 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54AC T11109 . . . J PAC KAG E 74A C T11109 . . . D OR N PAC KAG E • Flow-Through Architecture to Optimize PCB	OCR Scan	PDF	54ACT11109, 74ACT11109 TI0067-- D2957, 500-mA 300-mil
Untitled Abstract: No abstract text available Text: 54ACT11109,74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ D29S7, FEBRUARY 1987 - REVISED APRIL 1993 54ACT11109. . . J PACKAGE 74ACT11109 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible	OCR Scan	PDF	54ACT11109 74ACT11109 D29S7, 500-mA 300-mil
Untitled Abstract: No abstract text available Text: 54ACT11109,74ACT11109 DUALJ-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, FEBRUARY 1987 - REVISED APRIL 1993_ logic symbol* 1Q 1Q 2Q 2Q t This symbol is In accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.	OCR Scan	PDF	54ACT11109 74ACT11109 D2957, fl3bl723