ADC16DV160
Abstract: No abstract text available
Text: ADC16DV160 ADC16DV160 Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs Literature Number: SNAS488G ADC16DV160 Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs General Description The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to
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ADC16DV160
ADC16DV160
16-Bit,
SNAS488G
16-bit
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HIP-66
Abstract: No abstract text available
Text: FLASH AS8FLC1M32 FIGURE 1: PIN ASSIGNMENT Top View Hermetic, Multi-Chip Module (MCM) 32Mb, 1M x 32, 3.0Volt Boot Block FLASH Array Available via Applicable Specifications: • MIL-PRF-38534, Class H FEATURES • • • • • • • • • • • •
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AS8FLC1M32
MIL-PRF-38534,
64Kbyte
1Mx32,
AS8FLC1M32B
HIP-66
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K1115
Abstract: AD10242 AD9042 AD9632 D10A D11A OP279
Text: a Dual, 12-Bit, 40 MSPS MCM A/D Converter with Analog Input Signal Conditioning AD10242 The AD10242 operates with ± 5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital conversion. Each channel is completely independent, allowing
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12-Bit,
AD10242
AD10242
AD9042,
6/01--Data
AD9631
AD9632
K1115
AD9042
AD9632
D10A
D11A
OP279
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CY7C4255V
Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Text: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to
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CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
8K/16K/32K/64Kx18
CY7C4255/65/75/85V
CY7C42X5V
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
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512K32
Abstract: 9Q512K32 UT9Q512 UT9Q512K32
Text: Standard Products UT9Q512K32 16Megabit SRAM MCM Advanced Data Sheet January 15, 2001 FEATURES q 35ns maximum 5 volt supply address access time q Asynchronous operation for compatible with industry standard 512K x 8 SRAMs q TTL compatible inputs and output levels, three-state
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UT9Q512K32
16Megabit
30krads
300krads
16Mbit)
68-lead
10krad
30krad
512K32
9Q512K32
UT9Q512
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CY7C4205V
Abstract: CY7C4215V CY7C4225V CY7C4235V CY7C4245V CY7C42X5V CY7C4425V
Text: fax id: 5417 CY7C4425V/4205V/4215V PRELIMINARY CY7C4225V/4235V/4245V 64/256/512/1K/2K/4K x18 Low Voltage Synchronous FIFOs Features • 3.3V operation for low power consumption and easy integration into low voltage systems • High-speed, low-power, first-in first-out FIFO
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CY7C4425V/4205V/4215V
CY7C4225V/4235V/4245V
64/256/512/1K/2K/4K
CY7C4425V
CY7C4205V)
CY7C4215V)
CY7C4225V)
CY7C4235V)
CY7C4245V)
67-MHz
CY7C4205V
CY7C4215V
CY7C4225V
CY7C4235V
CY7C4245V
CY7C42X5V
CY7C4425V
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729h
Abstract: Z8*6421 Z8F642 PS019913-0305
Text: High Performance 8-Bit Microcontrollers Z8 Encore! 64K Series Product Specification PS019913-0305 Preliminary ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether
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PS019913-0305
729h
Z8*6421
Z8F642
PS019913-0305
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COP888GW
Abstract: V68A
Text: August 1996 COP888GW 8-Bit Microcontroller with Pulse Train Generators and Capture Modules General Description The COP888 family of microcontrollers uses an 8-bit single chip core architecture fabricated with National Semiconductor’s M2CMOS process technology. The COP888GW is a
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COP888GW
COP888
COP888GW
16-bit
V68A
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Untitled
Abstract: No abstract text available
Text: Standard Products QCOTSTM UT8Q512K32 16Megabit SRAM MCM Data Sheet January 21, 2002 FEATURES q 25ns maximum 3.3 volt supply address access time q MCM contains four (4) 512K x 8 industry-standard asynchronous SRAMs; the control architecture allows operation as 8, 16, 24, or 32-bit data width
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UT8Q512K32
16Megabit
32-bit
50krads
1E-10
68-lead
512K32
10krad
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Untitled
Abstract: No abstract text available
Text: Standard Products UT8ER512K32 Monolithic 16M RadHard SRAM Preliminary Data Sheet May 21, 2007 www.aeroflex.com/radhardsram INTRODUCTION FEATURES 20ns read, 10ns write maximum access times Functionally compatible with traditional 512K x 32 SRAM devices
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UT8ER512K32
100Krad
100MeV-cm2/mg
01x10-16
156KHz
0E14n/cm2
68-lead
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Dose
Abstract: No abstract text available
Text: Standard Products UT82CRH51A USART Preliminary Data Sheet December 9, 1999 FEATURES INTRODUCTION q Synchronous and asynchronous operation q Synchronous 5-8 bit characters; internal or external character synchronization; automatic synchronization insertion
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UT82CRH51A
MIL-STD-883
MIL-PRF-38535.
XLN-589
MIL-STD-1835.
36-pin
MILPRF-38535.
68-pin
Dose
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TMS320P14
Abstract: TMS320LC15
Text: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM
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TMS320C1x
SPRS009C
144/256-Word
TMS320E14/P14/E15/P15/E17/P17)
TMS320P14/P15/P17)
64K-Word
32-Bit
16-Bit
TMS320P14
TMS320LC15
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Untitled
Abstract: No abstract text available
Text: Standard Products QCOTSTM UT9Q512K32 16Megabit SRAM MCM Advanced Data Sheet August 6, 2001 FEATURES q 35ns maximum 5 volt supply address access time q Asynchronous operation for compatible with industry standard 512K x 8 SRAMs q TTL compatible inputs and output levels , three-state
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UT9Q512K32
16Megabit
50krads
1E-10
0E14n/cm2
68-lead
10krad
30krad
50krad
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Untitled
Abstract: No abstract text available
Text: Standard Products QCOTSTM UT8Q512K32 16Megabit SRAM MCM Preliminary Data Sheet June 20, 2001 FEATURES q 35ns maximum 3.3 volt supply address access time q MCM contains four (4) 512K x 8 industry-standard asynchronous SRAMs; the control architecture allows
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UT8Q512K32
16Megabit
32-bit
50krads
300krads
8E-11errors/bit-day,
0E14n/cm2
68-lead
10krad
50krad
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5962-0422
Abstract: No abstract text available
Text: Standard Products UT8CR512K32 16 Megabit SRAM Advanced Data Sheet March 2006 www.aeroflex.com/4MSRAM FEATURES 17ns maximum access time Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs CMOS compatible inputs and output levels, three-state
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UT8CR512K32
67E-7cm2/bit
0E14n/cm2
68-lead
5962-0422
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UT9Q512K32
Abstract: No abstract text available
Text: Standard Products UT9Q512K32E 16 Megabit RadTolerant SRAM MCM Data Sheet June 28, 2011 INTRODUCTION The UT9Q512K32E RadTol product is a high-performance 2M byte 16Mbit CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 x 8 bit SRAMs with a
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UT9Q512K32E
68-lead
UT9Q512K32
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Untitled
Abstract: No abstract text available
Text: 1 AUSTIN SEMICONDUCTOR, INC. AS8F2M 32 2MEG x 32 FLASH ~ FLASH MODULE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View SMD 5962-97531 MIL-STD-883 68LeadCQFP FEATURES ,/] OPTION • • n n in o ri Q /C < E C C < r< E |C J L D |o |> C < E < E C < r>
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MIL-STD-883
68LeadCQFP
150ns
AS8F2M32
DS000071
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tfm 1010
Abstract: G0b35
Text: 80C286 i l i HARRIS August 1995 High Performance Microprocessor With Memory Management and Protection 68LEadpga Features Pin Configurations • C om patib le with N M O S 8 0 2 8 6 Com ponent Pad View — As viewed from underside of the component when mounted on the board.
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80C286
5M-1982.
tfm 1010
G0b35
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10S8
Abstract: No abstract text available
Text: I AUSTIN SEMICONDUCTOR, INC. AS8F2M32 2MEG x 32 FLASH f FLASH MODULE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View SMD 5962-97531 MIL-STD-883 68LeadCQFP FEATURES ,/] OPTION • • n n in o ri Q /C < E C C < r< E |C J L D |o |> C < E < E C < r>
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AS8F2M32
MIL-STD-883
68LeadCQFP
150ns
DS000071
10S8
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TMS320P17
Abstract: d6151 filter lark eng 1D2T ltw 8 pin TMS320P14 TMS320LC15
Text: TMS320C1X DIGITAL SIGNAL PROCESSORS J A N U A H Y 1 9 8 7 — R E V IS E D J U L Y 1991 • Performance Up to 8.77 MIPs Commercial and Military Versions Available • All TMS320C1x Devices are Object Code Compatible Operating Free-Air Temperature . . . 0°C to 70°C
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TMS320C1X
144/256-Word
TMS320E14/P14/E15/P15/E17/P17)
TMS320P14/P15/P17)
64K-Word
32-Bit
TMS320C10
200-ns
TMS320C930)
TMS320P17
d6151
filter lark eng
1D2T
ltw 8 pin
TMS320P14
TMS320LC15
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Untitled
Abstract: No abstract text available
Text: PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO 4 FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. A ll mapping memory 10,240 bfts for both the MMU and BPU functions are Included on the chip.
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PACE1753
40MHz
MIL-STD-1750A
PACE1750A/AE
16-bit,
PACE1754
-962-8950503UX
5962-8950503YX
5962-8950503ZX
5962-8950504TX
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L9141
Abstract: FEATURES of TMS320 C 54 XX PROCESSOR lph 7670 TMS32020 TMS320 LA 7670 68-PIN TMS320C25 dummy 68pin DFDP-TI001
Text: T M S 32 0 SECOND GENERATION DIGITAL SIGNAL PROCESSORS MAY 6 8 -P IN GB • 100-n s Instruction Cycle Time • 5 4 4 Words of Programmable On-Chip Data RAM PIN GR ID A R R A Y C E R A M IC P A C K A G E T • 4K Words of On-Chip Program ROM • 128K Words of Data/Program Space
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TMS320
100-ns
32-Bit
16-Bit
68-Pin
SPRS010
L9141
FEATURES of TMS320 C 54 XX PROCESSOR
lph 7670
TMS32020
LA 7670
TMS320C25
dummy 68pin
DFDP-TI001
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31-oq
Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
Text: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342
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CY7C342
CY7C342B
128-Macrocell
CY7C342)
65-micron
CY7C342B)
68-pin
CY7C342/CY7C342B
CY7C342/
CY7C342B
31-oq
7C342-25
CY7C342-35HMB
7C342-35
OQ11
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CY7C381P
Abstract: CY7C381P-0JC CY7C381P-XJC CY7C381P-XJI CY7C382P CY7C383A CY7C385P 100-Pin CPGA Package Pin-Out Diagram
Text: CY7C381P CY7C382P CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns • Unparalleled FPGA performance for counters, data path, state machines,
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CY7C381P
CY7C382P
68-pin
69-pin
100-pin
16-bit
CY7C382Pâ
Y7C382Pâ
68-Lead
CY7C381P-0JC
CY7C381P-XJC
CY7C381P-XJI
CY7C382P
CY7C383A
CY7C385P
100-Pin CPGA Package Pin-Out Diagram
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