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    54AC11 Search Results

    54AC11 Result Highlights (4)

    Part ECAD Model Manufacturer Description Download Buy
    SNJ54AC11W Texas Instruments Triple 3-Input Positive-AND Gates 14-CFP -55 to 125 Visit Texas Instruments Buy
    SNJ54AC11J Texas Instruments Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125 Visit Texas Instruments Buy
    SNJ54AC11FK Texas Instruments Triple 3-Input Positive-AND Gates 20-LCCC -55 to 125 Visit Texas Instruments Buy
    CD54AC112F3A Texas Instruments Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset 16-CDIP -55 to 125 Visit Texas Instruments Buy
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    54AC11 Price and Stock

    Rochester Electronics LLC SNJ54AC11FK

    IC TRPL 3-INP
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    DigiKey SNJ54AC11FK Bulk 22
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    Texas Instruments CD54AC112F3A

    DUAL NEGATIVE EDGE TRIGGERED J-K
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    DigiKey CD54AC112F3A Tube
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    Rochester Electronics CD54AC112F3A 23 1
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    Rochester Electronics LLC CD54AC112F3A

    CD54AC112 DUAL NEGATIVE EDGE TRI
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    Rochester Electronics LLC JM54AC11SCA-RH

    IC GATE AND 3CH 3-INP 14CERDIP
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    DigiKey JM54AC11SCA-RH Bulk 1
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    Rochester Electronics LLC JM54AC11S2A-RH

    IC GATE AND 3CH 3-INP 20LCCC
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    Find more 54AC11 price and stock on Findchips.com

    54AC11 Datasheets (147)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54AC11 National Semiconductor Triple 3-Input AND Gate Original PDF
    54AC11000FK Texas Instruments Quad 2-input NAND Gate Scan PDF
    54AC11000FK Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Scan PDF
    54AC11000J Texas Instruments Quad 2-input NAND Gate Scan PDF
    54AC11000J Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Scan PDF
    54AC11002 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    54AC11002 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    54AC11002FK Texas Instruments IC NOR GATE QUAD 2IN CMOS 20LCCC Original PDF
    54AC11002J Texas Instruments IC NOR GATE QUAD 2IN CMOS 16CDIP Original PDF
    54AC11010 Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATES Original PDF
    54AC11010 Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATES Original PDF
    54AC11010FK Texas Instruments IC NAND GATE TRIPLE 3IN CMOS 20LCCC Original PDF
    54AC11010J Texas Instruments IC NAND GATE TRIPLE 3IN CMOS 16CDIP Original PDF
    54AC11011 Texas Instruments TRIPLE 3-INPUT POSITIVE-AND GATES Original PDF
    54AC11011 Texas Instruments TRIPLE 3-INPUT POSITIVE-AND GATES Original PDF
    54AC11011FK Texas Instruments IC AND GATE TRIPLE 3IN CMOS 20LCCC Original PDF
    54AC11011J Texas Instruments IC AND GATE TRIPLE 3IN CMOS 16CDIP Original PDF
    54AC11014 Texas Instruments HEX SCHMITT-TRIGGER INVERTERS Original PDF
    54AC11014 Texas Instruments HEX SCHMITT-TRIGGER INVERTERS Original PDF
    54AC11014FK Texas Instruments HEX SCHMITT-TRIGGER INVERTER Original PDF
    ...

    54AC11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74AC11533

    Abstract: No abstract text available
    Text: 54AC11533, 74AC11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS ą SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • • • 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE 8-Latches in a Single Package


    Original     		PDF 54AC11533, 74AC11533 54AC11533 74AC11533 SCAS004 D2957, 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW


    OCR Scan     		PDF 54AC11109, 74AC11109 TI0066-- D2957, 500-mA STD-883C 300-mil 54AC11109 74AC11109

    Untitled

    Abstract: No abstract text available
    Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to


    OCR Scan     		PDF 54AC11032, 74AC11032 TI0060-- D2957, 500-mA 300-mil 54AC11032

    Untitled

    Abstract: No abstract text available
    Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations


    OCR Scan     		PDF 54AC11021 74AC11021 D2957. 500-mA 300-mll

    Untitled

    Abstract: No abstract text available
    Text: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise


    OCR Scan     		PDF 54AC11002, 74AC11002 D2957, 500-mA 300-mil 54AC11002

    74AC11827

    Abstract: No abstract text available
    Text: 54AC11827, 74AC11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0155— 0 3 3 7 9 . NOVEMBER 1989— REVISED MARCH 1990 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 54AC11827 . . . JT PACKAGE 74AC11827 . . . DW OR NT PACKAGE TOP VIEW


    OCR Scan     		PDF 54AC11827, 74AC11827 10-BIT TI0155-- 500-mA 300-mll

    D2957

    Abstract: No abstract text available
    Text: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations


    OCR Scan     		PDF 500-mA 300-mll AC11240 AC11244, D2957

    74AC11520

    Abstract: No abstract text available
    Text: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations


    OCR Scan     		PDF 54AC11520 74AC11520 D2957, 500-mA 300-mil 54AC11520 74AC11S20.

    2a117

    Abstract: No abstract text available
    Text: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to


    OCR Scan     		PDF 54AC11158, 74AC11158 TI010 500-mA 300-mil 54AC11158 74AC11158 2a117

    Untitled

    Abstract: No abstract text available
    Text: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to


    OCR Scan     		PDF 74AC11004 TI0044-- D2957, 500-mA 300-mil 54AC11004 74AC11004

    Untitled

    Abstract: No abstract text available
    Text: 54AC11853, 74AC 11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS TI0157— D3473, MARCH 1990 54AC11B53 . . . JT PACKAGE 74AC11853 . . . DW OR NT PACKAGE High-Speed Bus Transceivers with Parity Generator/Checker TOP VIEW Parity Error Flag Open-Drain Output • Register for Storage of the Parity Error Flag


    OCR Scan     		PDF 54AC11853, TI0157-- D3473, 500-mA 300-mil 54AC11B53 74AC11853 54AC11853 74AC11853

    Untitled

    Abstract: No abstract text available
    Text: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [


    OCR Scan     		PDF 54AC11377, 74AC11377 TI0180-- D3420, 500-mA 300-mll 54AC11377

    54AC11181

    Abstract: TI018
    Text: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise


    OCR Scan     		PDF 54AC11181, 74AC11181 I0184-- 500-mA 300-mil 54AC11181 74AC11181 54AC11181 TI018

    74AC11873

    Abstract: No abstract text available
    Text: 54AC11873, 74AC11873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS • 54A C 11 8 73 . . . J T P A C K A G E 3-State Buffer-Type Outputs Drive Bus 74AC 11B73 . . . D W OR N T P A C K A G E Lines Directly TOP V IE W • Bus-Structured Pinout • Flow -Through A rchitecture O ptim izes PCB


    OCR Scan     		PDF 54AC11873, 74AC11873 11B73 500-m D3390,

    TI009

    Abstract: No abstract text available
    Text: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to


    OCR Scan     		PDF 54AC11643, I0095-- D2957, 500-mA 300-mil 54AC11643 74AC11643 TI009

    74AC108

    Abstract: so 54 t 74AC11066
    Text: 54AC11086, 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0152— D3375, N O VEM BER 1989 • Flow-Through Architecture to Optimize PCB Layout 54AC11086 . . . J PACKAGE 74AC11086 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to


    OCR Scan     		PDF 54AC11086, 74AC11086 TI0152-- D3375, 500-mA 300-mil 74AC108 so 54 t 74AC11066

    Untitled

    Abstract: No abstract text available
    Text: 54AC11074,74AC11074 DUAL D-TYPE POSUIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, D E C E M B E R 1986 - REVISED A P R IL 1983 54AC11074. . . J PACKAGE 74AC11074. . . D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout


    OCR Scan     		PDF 54AC11074 74AC11074 D2957, 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: 54AC11020,74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES D2957, MAHCH 1987-REVISEDAPRIL1993 54AC11020. . . J PACKAGE 74AC11020. . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise


    OCR Scan     		PDF 54AC11020 74AC11020 D2957, 1987-REVISEDAPRIL1993 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957. JUNE 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Pertormance Implanted CMOS 1-^m Process


    OCR Scan     		PDF 54AC11030, 74AC11030 D2957. 1987-R 500-mA 300-mll S4AC11032-85 54AC11030 D2957,

    TH 2267

    Abstract: 74AC11191
    Text: 54AC11191, 74AC11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS TI0151— D3426, MARCH 1990 • Single Down/Up Count Control Line 54AC11191 . . . J PACKAGE 74AC11191 . . . DW OR N PACKAGE • Look-Ahead Circuitry Enhances Speed of Cascaded Counters TOP VIEW


    OCR Scan     		PDF 54AC11191, 74AC11191 TI0151-- D3426, 500-mA 300-mil TH 2267

    19ba

    Abstract: No abstract text available
    Text: 54AC11238, 74AC11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D3103. APRIL 1988 - REVISED APRIL 1993 * * * * * * * * Designed Specifically for High-Speed Memory Decoders and Data Transmission


    OCR Scan     		PDF 54AC11238, 74AC11238 D3103. AC11138 500-mA 300-milTexas D3103, 19ba

    Untitled

    Abstract: No abstract text available
    Text: 54AC11027, 74AC11027 TRIPLE 3-INPUT POSITIVE-NOR GATES TI0056— D2957, JULY 1987—REVISED MARCH 1990 54AC11027 . . . J PACKAGE 74AC11027 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pln V c c and GND Configurations to


    OCR Scan     		PDF 54AC11027, 74AC11027 TI0056-- D2957, 1987--REVISED 500-mA 300-mil 54AC11027 74AC11027

    Untitled

    Abstract: No abstract text available
    Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D 2957, JULY 1987 - R EVISED APRIL 1993 * Flow-Through Architecture Optimizes PCB Layout 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Center-Pin Vcc and GND Configurations


    OCR Scan     		PDF 54AC11021 74AC11021 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: 54AC11175, 74AC11175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR T 10109— D3388, DECEMBER 1989— REVISED MARCH 1990 • Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators 5 4 A C 11 1 75 . . . J P A C K A G E 74A C 11175 . . . DW O R N PACKAGE


    OCR Scan     		PDF 54AC11175, 74AC11175 D3388, 500-mA 300-mil