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    5 INPUT OR GATE Search Results

    5 INPUT OR GATE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    TLX9188 Toshiba Electronic Devices & Storage Corporation Photocoupler (phototransistor output), DC input, 3750 Vrms, SO6, Automotive Visit Toshiba Electronic Devices & Storage Corporation
    TB67H480FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5/ PHASE input type Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5/ IN input type Visit Toshiba Electronic Devices & Storage Corporation
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation

    5 INPUT OR GATE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LVC1G386

    Abstract: 74LVC1G386GV 74LVC1G386GW
    Text: 74LVC1G386 3-input EXCLUSIVE-OR gate Rev. 02 — 3 September 2007 Product data sheet 1. General description The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function. The input can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices in a mixed 3.3 and 5 V environment.


    Original     		PDF 74LVC1G386 74LVC1G386 74LVC1G386GV 74LVC1G386GW

    IDT74LVC86A

    Abstract: No abstract text available
    Text: IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE INDUSTRIAL TEMPERATURE RANGE IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: This quadruple 2-input exclusive-OR gate is built using advanced dual


    Original     		PDF IDT74LVC86A LVC86A IDT74LVC86A

    Untitled

    Abstract: No abstract text available
    Text: 74LVC32A Quad 2-input OR gate Rev. 5 — 17 November 2011 Product data sheet 1. General description The 74LVC32A provides four 2-input OR gates. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.


    Original     		PDF 74LVC32A 74LVC32A JESD8-C/JESD36 JESD22-A114F JESD22-A115-B JESD22-C101E

    application note sot353-1 nxp

    Abstract: No abstract text available
    Text: 74LVC1G86 2-input EXCLUSIVE-OR gate Rev. 9 — 5 March 2012 Product data sheet 1. General description The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC1G86 74LVC1G86 JESD8B/JESD36 application note sot353-1 nxp

    Untitled

    Abstract: No abstract text available
    Text: 74LVC32A Quad 2-input OR gate Rev. 5 — 17 November 2011 Product data sheet 1. General description The 74LVC32A provides four 2-input OR gates. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.


    Original     		PDF 74LVC32A 74LVC32A JESD8-C/JESD36 JESD22-A114F JESD22-A115-B

    74LVC32A

    Abstract: 74LVC32ABQ 74LVC32AD 74LVC32ADB 74LVC32APW DHVQFN14 SSOP14 TSSOP14
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC32A Quad 2-input OR gate Product specification Supersedes data of 1997 Jun 30 2003 Jul 16 Philips Semiconductors Product specification Quad 2-input OR gate 74LVC32A FEATURES DESCRIPTION • 5 V tolerant inputs for interfacing with 5 V logic


    Original     		PDF 74LVC32A 74LVC32A SCA75 613507/03/pp16 74LVC32ABQ 74LVC32AD 74LVC32ADB 74LVC32APW DHVQFN14 SSOP14 TSSOP14

    Untitled

    Abstract: No abstract text available
    Text: Revised November 1999 100301 Low Power Triple 5-Input OR/NOR Gate General Description Features The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all outputs are buffered. • 23% power reduction of the 100101


    Original     		PDF 100301SC 100301PC 100301QC 100301QI 24-Lead MS-013,

    n24e

    Abstract: 100301PC 100301QC 100301QI 100301SC M24B MO-047 MS-013 V28A
    Text: Revised August 2000 100301 Low Power Triple 5-Input OR/NOR Gate General Description Features The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all outputs are buffered. • 23% power reduction of the 100101


    Original     		PDF 100301SC 24-Lead MS-013, 100301PC MS-010, 100301QC 28THOUT n24e 100301PC 100301QC 100301QI 100301SC M24B MO-047 MS-013 V28A

    74LVC86A

    Abstract: 74LVC86ABQ 74LVC86AD 74LVC86ADB 74LVC86APW SSOP14 TSSOP14
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC86A Quad 2-input EXCLUSIVE-OR gate Product specification Supersedes data of 2003 Nov 11 2004 Mar 04 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LVC86A FEATURES DESCRIPTION • 5 V tolerant inputs, for interfacing with 5 V logic


    Original     		PDF 74LVC86A 74LVC86A SCA76 R20/04/pp15 74LVC86ABQ 74LVC86AD 74LVC86ADB 74LVC86APW SSOP14 TSSOP14

    F100K

    Abstract: SY100S301 SY100S301FC SY100S301JC SY100S301JCTR F100K ECL book
    Text: TRIPLE 5-INPUT OR/NOR GATE SY100S301 DESCRIPTION FEATURES • Max. propagation delay of 750ps ■ IEE min. of –25mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option: VEE = –4.2V to –5.5V The SY100S301 is an ultra-fast triple 5-input OR/NOR


    Original     		PDF SY100S301 750ps SY100S301 F100K 24-pin 28-pin SY100S301FC F24-1 SY100S301JC J28-1 F100K SY100S301FC SY100S301JC SY100S301JCTR F100K ECL book

    fairchild ECL datasheet

    Abstract: diode d4c F100K SY100S301 SY100S301FC SY100S301JC SY100S301JCTR F100K ECL book
    Text: TRIPLE 5-INPUT OR/NOR GATE SY100S301 FINAL DESCRIPTION FEATURES • Max. propagation delay of 750ps ■ IEE min. of –25mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option: VEE = –4.2V to –5.5V The SY100S301 is an ultra-fast triple 5-input OR/NOR


    Original     		PDF SY100S301 750ps SY100S301 J28-1 F24-1 Ob0S301FC SY100S301JC SY100S301JCTR fairchild ECL datasheet diode d4c F100K SY100S301FC SY100S301JC SY100S301JCTR F100K ECL book

    74LVC1G86

    Abstract: 74LVC1G86GF 74LVC1G86GM 74LVC1G86GV 74LVC1G86GW JESD22-A114E
    Text: 74LVC1G86 2-input EXCLUSIVE-OR gate Rev. 06 — 18 July 2007 Product data sheet 1. General description The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC1G86 74LVC1G86 JESD8B/JESD36 74LVC1G86GF 74LVC1G86GM 74LVC1G86GV 74LVC1G86GW JESD22-A114E

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G32 Single 2-input OR gate Rev. 9 — 12 April 2012 Product data sheet 1. General description The 74LVC1G32 provides one 2-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.


    Original     		PDF 74LVC1G32 74LVC1G32

    Untitled

    Abstract: No abstract text available
    Text: 74LVC32A Quad 2-input OR gate Rev. 4 — 19 October 2011 Product data sheet 1. General description The 74LVC32A provides four 2-input OR gates. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.


    Original     		PDF 74LVC32A 74LVC32A JESD8-C/JESD36 JESD22-A114F JESD22-A115-B JESD22-C101E

    Untitled

    Abstract: No abstract text available
    Text: Section 3 Contents F100101 Triple 5-Input OR/NOR G a te . F100102 Quint 2-Input OR/NOR Gate .


    OCR Scan     		PDF F100101 F100102 F100104 F100107 F100112 F100113 F100182 F100183 F100250

    MC10109

    Abstract: No abstract text available
    Text: MOTOROLA MC10109 DUAL 4-5-INPUT "OR/NOR" GATE DUAL 4-5-INPUT “OR/NOR" GATE The MC10109 is a dual 4-5 Input OR/NOR gate. PD = 30 m W typ/gate No Load t pd = 2.0 ns typ t r, tf = 2.0 ns typ (20%—80%) L SUFFIX CERAMIC PACKAGE CASE 620 1 P SUFFIX PLASTIC PACKAGE


    OCR Scan     		PDF MC10109 MC10109

    100352

    Abstract: No abstract text available
    Text: * Section 2 Contents 100201 Low Power 2-Input OR/NOR G ate/Inverter. 100301 Low Power Triple 5-Input OR/NOR G a te .


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: * TRIPLE 5-INPUT OR/NOR GATE SYNERGY SEMICONDUCTOR SY100S301 SY101S301 PRELIMINARY DESCRIPTION FEATURES • Max. Propagation Delay of 700 ps. The SY100/101S301 is an ultra-fast triple 5-input OR/NOR gate designed for use in high performance ECL systems. The inputs on


    OCR Scan     		PDF SY100S301 SY101S301 SY100/101S301 SY101S301

    100101DC

    Abstract: No abstract text available
    Text: 100101 National Semiconductor F100101 Triple 5-Input OR/NOR Gate General Description The F100101 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 k fl pull-down resistors and all outputs are buffered. Refer to the F100301 datasheet for: PCC packaging


    OCR Scan     		PDF F100101 F100301 TL/F/9835-3 24-Pin 24-Pln TL/F/9835-5 Tl/F/9835-6 100101DC

    shbb

    Abstract: 100118F 100118Y lt 748
    Text: Signetics 100118 Gate Quint 2-4-4-4-5-Input OR-AND Gate Product Specification ECL Products DESCRIPTION The 100118 is a 5-wide OR-AND 2-4-4­ 4-5 input Gate with true and complemen­ tary outputs. TYPE TY PIC AL PROPAGATION DELAY TYPIC AL SUPPLY CURRENT 100118


    OCR Scan     		PDF 100118F 100118Y Do-D18 740mVp-p 500ns shbb 100118F 100118Y lt 748

    Untitled

    Abstract: No abstract text available
    Text: NATIONAL SEflICOND LOGIC 31E D hsoiiaa 007104=1 t T-M 5 -7-Z -O O IOT National SjA Semiconductor F100101 Triple 5-input OR/NOR Gate General Description The F100101 is a monolithic triple 5-input OR/NOR gate. All Inputs have 50 k il pull-down resistors and all outputs are


    OCR Scan     		PDF F100101 F100301 24-Pln

    Untitled

    Abstract: No abstract text available
    Text: 100101 KgM National ÉjA Semiconductor F100101 Triple 5-Input OR/NOR Gate General Description TheF100101 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 k il pull-down resistors and all outputs are buffered. Ordering~Code: Refer to the F100301 datasheet for:


    OCR Scan     		PDF F100101 TheF100101 F100301 TL/F/9035-3 24-Pln 24-Pin TL/F/9835-5 TL/F/9835-6

    SP1600 SERIES ECL III

    Abstract: SP1600
    Text: SP1664/5 O PLESSEY SP1600 SERIES SEMICONDUCTORS ECL III SP1664 SP1665 HIGH Z (LOWZ) QUAD 2-INPUT OR GATE The SP1664/5 comprises four 2-input OR gating functions in a single package. An internal bias reference voltage ensures that the threshold point remains in the


    OCR Scan     		PDF SP1664/5 SP1600 SP1664 SP1665 SP1664/5 SP1600 SERIES ECL III

    DALE R 01F

    Abstract: 5962-9152801MXA F301
    Text: N ation al Semiconductor MICROCIRCUIT DATA SHEET Wmm MN100301-X REV ICO Last Major Revision Date: 05/09/96 LOW P OWER TRIPLE 5-INPUT OR/NOR GATE General Description The 100301 is a monolithic triple 5-input OR/NOR gate. resistors and all outputs are buffered.


    OCR Scan     		PDF MN100301-X 01DMQB 01FMQB MN100301â J24ERJ P000033A P000034A DALE R 01F 5962-9152801MXA F301