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    CY7C1392V18

    Abstract: CY7C1393V18 CY7C1394V18
    Text: 392V18 392V18 CY7C1393V18 CY7C1394V18 ADVANCE INFORMATION 18-Mb SRAM with DDR-II SIO Architecture Features Functional Description • 18-Mb Density 2M x 8, 1M x 18, 512K x 36 — Supports concurrent transactions • 300-MHz Clock for High Bandwidth


    Original     		PDF 392V18 CY7C1392V18 CY7C1393V18 CY7C1394V18 18-Mb 300-MHz CY7C1392V18 CY7C1393V18 CY7C1394V18