NEC 2561
Abstract: 2565 nec NEC 2562 nec 2565 GAL20V8 GAL20V8Z GAL20V8Z-12QJ GAL20V8Z-12QP GAL20V8Z-15QP GAL20V8ZD
Text: GAL20V8Z GAL20V8ZD Zero Power E2CMOS PLD Features Functional Block Diagram • ZERO POWER E2CMOS TECHNOLOGY — 100µA Standby Current — Input Transition Detection on GAL20V8Z — Dedicated Power-down Pin on GAL20V8ZD — Input and Output Latching During Power Down
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GAL20V8Z
GAL20V8ZD
NEC 2561
2565 nec
NEC 2562
nec 2565
GAL20V8
GAL20V8Z
GAL20V8Z-12QJ
GAL20V8Z-12QP
GAL20V8Z-15QP
GAL20V8ZD
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20V8Q
Abstract: SL06 20V8H-15 20V8 GAL20V8 PAL20R8 PALCE20V8 PD3024 pal20v8
Text: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability
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H-5/7/10/15/25,
Q-10/15/25
H-15/25,
Q-20/25
PALCE20V8
24-Pin
PD3024)
28-Pin
20V8Q
SL06
20V8H-15
20V8
GAL20V8
PAL20R8
PD3024
pal20v8
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P20V8
Abstract: G20V8 GAL20V8B GAL20V8B-10LP GAL20V8B-15LPI IC of XOR GATE 20V8 GAL20V8 GAL20V8B-7LJ GAL20V8C
Text: GAL20V8 High Performance E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 166 MHz — 4 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology
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PDF
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GAL20V8
Tested/100%
P20V8
G20V8
GAL20V8B
GAL20V8B-10LP
GAL20V8B-15LPI
IC of XOR GATE
20V8
GAL20V8
GAL20V8B-7LJ
GAL20V8C
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12L10
Abstract: 16L6 20C1
Text: 2 4 -P in P A L / H A L D e v ice s 12L10 E ^7^ 3 E =E> 3 E = t> 3 E =E> 3 E =E> 3 E = 0 3 E :£ > 3 E = 0 3 E =E> 3 E = 0 3 E = I> 3 E 3 - - AND LOGIC nnnnv - - - - 1 20L2 14L8 E 3 d E E E E E E E E E E E AND LOGIC ARRAY ¡3 =L> 3 = 0 3 =L> IE =T> 3 = o 13
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
12L10
16L6
20C1
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12L10
Abstract: 16L6 20C1
Text: 24-Pin P A L / H A L Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E= I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E ¡3 3 3 AND LOGIC ARRAY 22] =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID AND LOGIC
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
12L10
16L6
20C1
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12L10
Abstract: 16L6 20C1
Text: 2 4 -P in P A L / H A L D e v ice s 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E= I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E E 3 AND LOGIC ARRAY ¡3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID ¡3 1
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
12L10
16L6
20C1
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12L10
Abstract: 16l6 14l8 Monolithic Memories pal18l4 islez 18L4 20C1 PAL12L10 PAL14L8 PAL16L6
Text: Small 24 Series 12L10, 14L8, 16L6, 18L4, 20L2, 20C1 Small 24 Series PAL12L10 14L8 PAL16L6 PAL18L4 PAL20L2 PAL20C1 INPUTS OUTPUTS POLARITY T rd ns Ice <mA) 12 14 16 18 20 20 10 8 6 4 2 2 LOW LOW LOW LOW LOW LOW 40 40 40 40 40 40 100 100 100 100 100 100
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OCR Scan
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PDF
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12L10,
PAL12L10
PAL14L8
PAL16L6
PAL18L4
PAL20L2
PAL20C1
24-pin
12L10
12L10
16l6
14l8
Monolithic Memories pal18l4
islez
18L4
20C1
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12L10
Abstract: 16L6 20C1 20X10
Text: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E=t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E=I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 ID O AND LOGIC ARRAY 13 E
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
20X10
20L10
20LID
12L10
16L6
20C1
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20L8B
Abstract: 12L10 16L6 20C1 id3-e
Text: 24-P in P A L /H A L Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E = I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E 3 3 AND LOGIC ARRAY =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID AND LOGIC ARRAY
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
20L8B,
20R6B,
20R4B
20L8B
12L10
16L6
20C1
id3-e
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20l10
Abstract: 20X4 20C1 12L10 16L6
Text: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E=t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E=I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 ID O AND LOGIC ARRAY 13 E
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
20LID
20L10
20l10
20X4
20C1
12L10
16L6
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20x8
Abstract: 12L10 16L6 20C1
Text: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E=t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E =I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 ID O S3 13 AND LOGIC ARRAY
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
20X10
20L10
20LID
20x8
12L10
16L6
20C1
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12L10
Abstract: 16L6 20C1
Text: 2 4 -P in P A L / H A L D e v ice s 12L10 E ^7^ 3 E =E> 3 E = t> 3 E =E> 3 E =E> 3 E = 0 3 E :£ > 3 E = 0 3 E =E> 3 E = 0 3 E = I> 3 E 3 - - AND LOGIC nnnnv - - - - 1 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
U--16--
12L10
16L6
20C1
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12L10
Abstract: 16L6 20C1
Text: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E=t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E=I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 ID O AND LOGIC ARRAY 13 E
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
12L10
16L6
20C1
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12L10
Abstract: 16L6 20C1
Text: 2 4 -P in P A L /H A L Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E= I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID ¡3 22] AND
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
12L10
16L6
20C1
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20L8A
Abstract: 20R4A 12L10 16L6 20C1
Text: 24-P in P A L /H A L Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 E - nnnnv 3 E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E = I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID AND LOGIC ARRAY
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
20R6A
20R4A
20L8A
20L8A
12L10
16L6
20C1
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Untitled
Abstract: No abstract text available
Text: Small 24 Series 12L10, 14L8, 16L6, 18L4, 20L2, 20C1 Small 24 Series PAL12L10 14L8 PAL16L6 PAL18L4 PAL20L2 PAL20C1 INPUTS O U T PU T S POLARITY TpD ns (mA) 12 14 16 18 20 20 10 8 6 4 2 2 LOW LOW LOW LOW LOW LOW 40 40 40 40 40 40 100 100 100 100 100 100
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OCR Scan
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PDF
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12L10,
PAL12L10
PAL14L8
PAL16L6
PAL18L4
PAL20L2
PAL20C1
24-pin
12L10
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20l8a-2
Abstract: 12L10 16L6 20C1
Text: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E = I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID AND LOGIC ARRAY 13
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OCR Scan
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PDF
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24-Pin
12L10
20L10/A
20X1O/A
20X8/A
20X4/A
20L8A/A-2/B
20L8A-2
20R6A-2
20R4A-2
12L10
16L6
20C1
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aeg diode Si 11 K
Abstract: aeg diode Si 11 aeg Diode D6 aeg diode Si 11 n
Text: ADV MICRO P LA / P L E / A R R AY S It D E | 02S75EL. OOSTMST Û T-46-13-47 Zero Power CMOS Hard Array Logic ZHAL 24A Series Features/Benefits Ordering information • Zero standby power PART NUM BER • Low power operation PACKAGE • High-speed C M O S technology
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OCR Scan
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PDF
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02S75EL.
T-46-13-47
ZHALTM24A
24-pln
28-pln
ZHAL12L10A
ZHAL14L8A
ZHAL16L6A
ZHAL18L4A
aeg diode Si 11 K
aeg diode Si 11
aeg Diode D6
aeg diode Si 11 n
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Untitled
Abstract: No abstract text available
Text: Lattice GAL20LV8 Low Voltage E2CMOS PLD Generic Array Logic ; ; Semiconductor •■ Corporation Functional Block Diagram HIGH PERFORMANCE E2CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output
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OCR Scan
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PDF
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GAL20LV8
Tested/100%
100ms)
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GAL Gate Array Logic
Abstract: GAL20V6
Text: GAL20V8 3 National Semiconductor GAL20V8 Generic Array Logic General Description The NSC E^CMOStm GAL device combines a high per formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable
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OCR Scan
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PDF
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GAL20V8
GAL20V8
24-pin
GAL20V8;
28-lead
GAL Gate Array Logic
GAL20V6
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Untitled
Abstract: No abstract text available
Text: Features Industry Standard Architecture - Emulates Many 24-Pin PALs - Low Cost Easy-to-Use Software Tools High-Speed Electrically Erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-Pin Delay Several Power Saving Options Device lcc, Stand-By lcc, Active
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OCR Scan
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PDF
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24-Pin
ATF20V8B
ATF20V8BQ
ATF20V8BQL
24-Lead,
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Untitled
Abstract: No abstract text available
Text: Features Industry Standard Architecture - Emulates Many 24-pin PALs - Low-cost Easy-to-use Software Tools High-speed Electrically-erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-pin Delay Several Power Saving Options Device lcc, Standby lcc, Active
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OCR Scan
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PDF
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24-pin
ATF20V8B
ATF20V8BQ
ATF20V8BQL
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Untitled
Abstract: No abstract text available
Text: GAL20LV8ZD iüLattice Low Voltage, Zero Power E2CMOS PLD Generic Array Logic ! SS! ! SSemiconductor •■■■■■ Corporation Features • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Com patible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices
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OCR Scan
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PDF
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GAL20LV8ZD
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Untitled
Abstract: No abstract text available
Text: GAL20V8 Lattice High Performance E2CMOS PLD Generic Array Logic ; Semiconductor I Corporation Functional Block Diagram Features HIGH PERFORMANCE E2CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 1 6 6 MHz — 4 ns Maximum from Clock Input to Data Output
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OCR Scan
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PDF
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GAL20V8
Tested/100%
100ms)
20V8C:
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