ecl 10K
Abstract: RCD Components E1001 E1004 E1008 E103 E105 SCHEMAT
Text: PRELIMINARY ECL DIGITAL DELAY LINES - 5-41-5 - ECL 10K INTERFACED - 5-41-5 - ECL 100K INTERFACED FEATURES TYPE E105 - ECL 10K 5 TAP Tap Delay nS 3 20 4 25 5 30 6 2X Total Delay Pulse Spacing 5X Total Delay -1.0V provided by open emitter ECL 10K gate
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3A5 tube
Abstract: SM DELAY LINES 3H-25
Text: PROGRAMMABLE ECL DELAY LINES EC3A 3 BIT 10K ECL LOGIC EC3H 3 BIT 10KH ECL LOGIC RoHS RESISTORS CAPACITORS COILS DELAY LINES Term.W is RoHS compliant Incremental delays of 0.5nS to 10nS Choice of 16-pin DIP or SM package 10K E C L RC D P/N 10K H E C L RC D P/N
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16-pin
3H-12
3H-10
FA112
GF-061.
3A5 tube
SM DELAY LINES
3H-25
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DECL
Abstract: decl_fm FECL-10 FECL-15 FECL-20 FECL-25 FECL-50 MECL-10 MECL-15 MECL-20
Text: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL • Single: FECL • Triple: MECL Electrical Specifications at 25OC Delay Single Triple ns 10K P/N 10K P/N FECL-3 MECL-3 3 ± 0.5 FECL-4 MECL-4 4 ± 0.5 FECL-5 MECL-5 5 ± 0.5 FECL-6 MECL-6 6 ± 0.75
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16-Pin
FECL-10
MECL-10
FECL-15
MECL-15
FECL-20
MECL-20
FECL-25
MECL-25
FECL-50
DECL
decl_fm
FECL-10
FECL-15
FECL-20
FECL-25
FECL-50
MECL-10
MECL-15
MECL-20
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eclpw
Abstract: pulse width generator
Text: 10K / 10KH ECL Logic Pulse Width Control Modules Electrical Specifications at 25OC Electrical Specifications at 25OC 10KH ECL Pulse Width Generator Modules 10K ECL Pulse Width Generator Modules Maximum Freq. MHz 77.0 67.0 59.0 53.0 48.0 43.0 31.0 23.0 19.0
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ECLPWG-10
ECLPWG-15
ECLPWG-20
ECLPWG-25
ECLPWG-30
ECLPWG-40
ECLPWG-50
ECLPWG-60
ECLPWG-75
ECLPWG-100
eclpw
pulse width generator
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SM2400
Abstract: No abstract text available
Text: FULL SIZE D.I.L M package CRYSTAL OSCILLATORS 10K ECL -5.2V M1400, M1444, M2400, M2444, Thru-Hole / Gull Wing M1436, M1445, M2436, M2445 These models which use 10K ECL -5.2V logic are not recommended for new designs. Suggested models are M1600 series that use
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M1400,
M1444,
M2400,
M2444,
M1436,
M1445,
M2436,
M2445
M1600
M2910
SM2400
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Untitled
Abstract: No abstract text available
Text: DP8480A DP8480A 10k ECL to TTL Level Translator with Latch Literature Number: SNOSBN8A DP8480A 10k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs
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DP8480A
DP8480A
16-pin
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Untitled
Abstract: No abstract text available
Text: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL • Single: FECL • Triple: MECL Electrical Specifications at 25°C Delay Single Triple 10K P/N ns 10K P/N 3 ±0.5 4 ± 0.5 5 ±0.5 6 ± 0.75 7 ±0.75 8 ±0.8 9 ± 1.0 10 ± 1.0 15 ± 1.5 20 ± 1.5
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16-Pin
FECL-10
FECL-15
FECL-20
FECL-25
FECL-50
FECL-60
FECL-75
FECL-100
MECL-10
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FECL250
Abstract: No abstract text available
Text: RHOMBUS INDUSTRIES INC M5E D • 772MR20 Ü0Q02S1 Ö ■ RHBT-H'J- i3 10K & 100K ECL BUFFERED DELAY MODULES GENERAL OPERATING SPECIFICATIONS JQK.ECL TEST CONDITIONS 10K ECL: VEESupply V o lta g e .-5.20 ± 0.25 VDC
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772MR20
0Q02S1
265jiAmax.
DECL-225
DECL-250
DECL-275
DECL-300
DECL-325
CL-350
DECL-375
FECL250
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Untitled
Abstract: No abstract text available
Text: ECL Surface-Mount Delay Modules ► 10k ECL logic levels. 10k ECL Programmable Delay Modules Part No. GECLPG301MX GECLPG302MX GECLPG303MX GECLPG304MX GECLPG305MX GEGLPG306MX GECLPG307MX GECLPG308MX GECLPG309MX GECLPG310MX Step Delay ns ± ns Max. Delay ns ± ns
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GECLPG301MX
GECLPG302MX
GECLPG303MX
GECLPG304MX
GECLPG305MX
GEGLPG306MX
GECLPG307MX
GECLPG308MX
GECLPG309MX
GECLPG310MX
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Untitled
Abstract: No abstract text available
Text: DP8480 10K ECL-TO-TTL LEVEL TRANSLATOR WITH LATCH SLLS035B - D3058, NOVEMBER 1987 - REVISED FEBRUARY 1993 * ECL Control Inputs * 3-State Outputs N PACKAGE TOP VIEW * 10K ECL Input Compatible v Ee * Direct Replacement for National Semiconductor DP8480 [ 1
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DP8480
SLLS035B
D3058,
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Untitled
Abstract: No abstract text available
Text: bel/ defining a degree of excellence DIGITAL DELAY LINE SERIES 0451 ECL 10K PROGRAMMABLE LOGIC DELAY MODULE 3 BIT TECHNICAL INFORMATION TEST CONDITIONS Driving Signal Pulse Width Pulse Period Supply Voltage, Vee Output Terminations ECL 10K Buffer 1.5 x Total Delay
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432-0463/TW
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Untitled
Abstract: No abstract text available
Text: bel/ defining a degree of excellence DIGITAL DELAY LINE SERIES 0451 ECL 10K PROGRAMMABLE LOGIC DELAY MODULE 3 BIT TECHNICAL INFORMATION TEST CONDITIONS Driving Signal Pulse Width Pulse Period Supply Voltage, Vee Output Terminations ECL 10K Buffer 1.5 x Total Delay
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432-0463/TWX
710-730-5301/FAX
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Untitled
Abstract: No abstract text available
Text: bel/.defining a degree of excellence DIGITAL DELAY LINE SERIES 0451 ECL 10K PROGRAMMABLE LOGIC DELAY MODULE 3 BIT TECHNICAL INFORMATION TEST CONDITIONS Driving Signal Pulse Width Pulse Period Supply Vbltage, Vee Output Terminations ECL 10K Buffer 1.5 x Total Delay
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432-0463/TWX
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DP8480
Abstract: D3058
Text: DP8480 10K ECL-TO-TTL LEVEL TRANSLATOR WITH LATCH SLLS035B - D3058, N OVEMBER 1987 - REVISED FEBRUARY 1993 ECL Control Inputs 3-State Outputs 10K ECL Input Compatible N PACKAGE fTOP VIEW Ve e [ 1 DO [ 2 Direct Replacement for National Semiconductor DP8480
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PDF
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DP8480
SLLS035B
D3058,
D3058
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Untitled
Abstract: No abstract text available
Text: NEC JUPD10500 262,144 X 1-Bit 10K BiCMOS ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configuration ThepPD10500 is a very high-speed BiCMOS RAM with a 10K ECL interface. Its unique design uses blended CMOS and bipolar peripheral circuits and N-channel
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24-Pin
uPD10500
ThepPD10500
300-mil,
/iPD10500
83IH-5947B
83IH-54480
pPD10500
3IH6144B
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Untitled
Abstract: No abstract text available
Text: SEC fiPB10A484 4,096 X 4-Blt 10K ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configurations The mPB10A484 is a very high-speed 10K interface ECL RAM organized as 4,096 words by 4 bits with nonlnverted, open-emitter outputs. Two versions with access
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uPB10A484
mPB10A484
pPB10A4B4
400-mil,
28-pln
28-Pin
096-word
fiPB10A484
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Untitled
Abstract: No abstract text available
Text: NEC fiPD10504 65,536 x 4-Bit 10K BiCMOS ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configuration The /JPD10504 is a very high-speed BiCMOS RAM with a 10K ECL interface. Its unique design uses blended CMOS and bipolar peripheral circuits and N-channel
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fiPD10504
/JPD10504
PD10504
400-mil,
32-pin
31H-6036B
83YL-7192B
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Untitled
Abstract: No abstract text available
Text: NEC ffPB10474E 1,024 X 4-Bit 10K ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configuration The ¿JPB10474E is a very high-speed 10K interface ECL RAM organized as 1,024 words by 4 bits and designed with noninverted, open-emitter outputs and low power
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uPB10474E
400-mil,
24-pin
024-word
ffPB10474E
83Yput
JHPB10474E
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Untitled
Abstract: No abstract text available
Text: NEC pPB10474E 1024 X 4-Bit 10K ECL RAM NEC Electronics Inc. Description Pin Configurations The /UPB10474E is a very-high-speed 10K interface ECL RAM organized as 1024 words by 4 bits and designed with noninverted, open-emitter outputs and low power consumption.
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uPB10474E
/UPB10474E
24-Pin
HPB10474E
1024-word
83FM-6646A
fiPB10474E
83IH-6164B
pPB10474E
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Untitled
Abstract: No abstract text available
Text: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL Single: FECL Triple: MECL * * Electrical Specifications at 25°C_ 10K ECL 5 Tap P/N Tap Delay Tolerances +/- 5% or 1.5ns +/- 0.8ns <10ns Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5
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16-Pin
DECL-10
DECL-12
DECL-15
DECL-20
DECL-25
DECL-30
DECL-35
DECL-40
DECL-45
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Untitled
Abstract: No abstract text available
Text: 10K/10KH ECL Logic Pulse Width Control Modules Electrical Specifications at 25°C 10K ECL Pulse Width Generator Modules Part Number > Triggered by the input's rising edge input pulse width 5 ns, min. , a pulse of specified width will be generated at the output
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10K/10KH
ECLPWG-10
ECLPWG-15
ECLPWG-20
ECLPWG-25
ECLPWG-30
ECLPWG-40
ECLPWG-50
ECLPWG-60
ECLPWG-75
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Untitled
Abstract: No abstract text available
Text: NEC pPD10500 262,144 x 1-Bit 10K BiCMOS ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configuration ThepPD10500 is a very high-speed BiCMOS RAM with a 10K ECL interface. Its unique design uses blended CMOS and bipolar peripheral circuits and N-channel
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OCR Scan
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PDF
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pPD10500
ThepPD10500
300-mil,
24-pin
/1PD10500
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Untitled
Abstract: No abstract text available
Text: NEC /iPB10484A 4,096 X 4-BIT 10K ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configurations The /tPB10484A is a very high-speed 10K interface ECL RAM. It is organized as 4,096 words by 4 bits and designed with noninverted, open-emltter outputs and
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uPB10484A
/iPB10484A
400-mil,
28-pin
096-word
pPB10484A
83IH-5947B
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Untitled
Abstract: No abstract text available
Text: 10K ECL Delay Modules 10k ECL Delay Modules Tap Delays ns Part No. T«1 T02 T03 V T05 Output Rise Time ECLDL025 ECLDL050 ECLDL075 ECLDL100 ECLDL125 ECLDL150 ECLDL200 ECLDL250 ECLDL300 ECLDL350 ECLDL400 ECLDL450 ECLDL500 5 10 15 20 25 30 40 50 60 70 80 90
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16-pin
ECLDL025
ECLDL050
ECLDL075
ECLDL100
ECLDL125
ECLDL150
ECLDL200
ECLDL250
ECLDL300
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